Lines Matching +full:0 +full:xe000a000
28 #size-cells = <0>;
30 PowerPC,8377@0 {
32 reg = <0x0>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
45 reg = <0x00000000 0x20000000>; // 512MB at 0
52 reg = <0xe0005000 0x1000>;
53 interrupts = <77 0x8>;
57 ranges = <0 0x0 0xfe000000 0x02000000
58 1 0x0 0xf8000000 0x00008000
59 3 0x0 0xe0600000 0x00008000>;
61 flash@0,0 {
65 reg = <0 0x0 0x2000000>;
69 u-boot@0 {
70 reg = <0x0 0x100000>;
75 reg = <0x100000 0x800000>;
79 reg = <0x1d00000 0x200000>;
83 reg = <0x1f00000 0x100000>;
87 bcsr@1,0 {
88 reg = <1 0x0 0x8000>;
92 nand@3,0 {
97 reg = <3 0x0 0x8000>;
99 u-boot@0 {
100 reg = <0x0 0x100000>;
105 reg = <0x100000 0x300000>;
109 reg = <0x400000 0x1c00000>;
119 ranges = <0x0 0xe0000000 0x00100000>;
120 reg = <0xe0000000 0x00000200>;
121 bus-frequency = <0>;
125 reg = <0x200 0x100>;
132 sleep = <&pmc 0x0c000000>;
137 #size-cells = <0>;
138 cell-index = <0>;
140 reg = <0x3000 0x100>;
141 interrupts = <14 0x8>;
147 reg = <0x68>;
148 interrupts = <19 0x8>;
155 reg = <0x2e000 0x1000>;
156 interrupts = <42 0x8>;
160 clock-frequency = <0>;
166 #size-cells = <0>;
169 reg = <0x3100 0x100>;
170 interrupts = <15 0x8>;
176 cell-index = <0>;
178 reg = <0x7000 0x1000>;
179 interrupts = <16 0x8>;
186 reg = <0x23000 0x1000>;
188 #size-cells = <0>;
190 interrupts = <38 0x8>;
193 sleep = <&pmc 0x00c00000>;
199 cell-index = <0>;
203 reg = <0x24000 0x1000>;
204 ranges = <0x0 0x24000 0x1000>;
206 interrupts = <32 0x8 33 0x8 34 0x8>;
211 sleep = <&pmc 0xc0000000>;
216 #size-cells = <0>;
218 reg = <0x520 0x20>;
222 interrupts = <17 0x8>;
223 reg = <0x2>;
228 interrupts = <18 0x8>;
229 reg = <0x3>;
233 reg = <0x11>;
246 reg = <0x25000 0x1000>;
247 ranges = <0x0 0x25000 0x1000>;
249 interrupts = <35 0x8 36 0x8 37 0x8>;
254 sleep = <&pmc 0x30000000>;
259 #size-cells = <0>;
261 reg = <0x520 0x20>;
264 reg = <0x11>;
271 cell-index = <0>;
274 reg = <0x4500 0x100>;
275 clock-frequency = <0>;
276 interrupts = <9 0x8>;
284 reg = <0x4600 0x100>;
285 clock-frequency = <0>;
286 interrupts = <10 0x8>;
294 reg = <0x82a8 4>;
295 ranges = <0 0x8100 0x1a8>;
297 interrupts = <0x47 8>;
298 cell-index = <0>;
299 dma-channel@0 {
301 reg = <0 0x80>;
302 cell-index = <0>;
304 interrupts = <0x47 8>;
308 reg = <0x80 0x80>;
311 interrupts = <0x47 8>;
315 reg = <0x100 0x80>;
318 interrupts = <0x47 8>;
322 reg = <0x180 0x28>;
325 interrupts = <0x47 8>;
330 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
331 "fsl,sec2.1", "fsl,sec2.0";
332 reg = <0x30000 0x10000>;
333 interrupts = <11 0x8>;
337 fsl,exec-units-mask = <0x9fe>;
338 fsl,descriptor-types-mask = <0x3ab0ebf>;
339 sleep = <&pmc 0x03000000>;
344 reg = <0x18000 0x1000>;
345 interrupts = <44 0x8>;
347 sleep = <&pmc 0x000000c0>;
352 reg = <0x19000 0x1000>;
353 interrupts = <45 0x8>;
355 sleep = <&pmc 0x00000030>;
367 #address-cells = <0>;
369 reg = <0x700 0x100>;
374 reg = <0xb00 0x100 0xa00 0x100>;
375 interrupts = <80 0x8>;
381 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
384 /* IDSEL 0x11 */
385 0x8800 0x0 0x0 0x1 &ipic 20 0x8
386 0x8800 0x0 0x0 0x2 &ipic 21 0x8
387 0x8800 0x0 0x0 0x3 &ipic 22 0x8
388 0x8800 0x0 0x0 0x4 &ipic 23 0x8
390 /* IDSEL 0x12 */
391 0x9000 0x0 0x0 0x1 &ipic 22 0x8
392 0x9000 0x0 0x0 0x2 &ipic 23 0x8
393 0x9000 0x0 0x0 0x3 &ipic 20 0x8
394 0x9000 0x0 0x0 0x4 &ipic 21 0x8
396 /* IDSEL 0x13 */
397 0x9800 0x0 0x0 0x1 &ipic 23 0x8
398 0x9800 0x0 0x0 0x2 &ipic 20 0x8
399 0x9800 0x0 0x0 0x3 &ipic 21 0x8
400 0x9800 0x0 0x0 0x4 &ipic 22 0x8
402 /* IDSEL 0x15 */
403 0xa800 0x0 0x0 0x1 &ipic 20 0x8
404 0xa800 0x0 0x0 0x2 &ipic 21 0x8
405 0xa800 0x0 0x0 0x3 &ipic 22 0x8
406 0xa800 0x0 0x0 0x4 &ipic 23 0x8
408 /* IDSEL 0x16 */
409 0xb000 0x0 0x0 0x1 &ipic 23 0x8
410 0xb000 0x0 0x0 0x2 &ipic 20 0x8
411 0xb000 0x0 0x0 0x3 &ipic 21 0x8
412 0xb000 0x0 0x0 0x4 &ipic 22 0x8
414 /* IDSEL 0x17 */
415 0xb800 0x0 0x0 0x1 &ipic 22 0x8
416 0xb800 0x0 0x0 0x2 &ipic 23 0x8
417 0xb800 0x0 0x0 0x3 &ipic 20 0x8
418 0xb800 0x0 0x0 0x4 &ipic 21 0x8
420 /* IDSEL 0x18 */
421 0xc000 0x0 0x0 0x1 &ipic 21 0x8
422 0xc000 0x0 0x0 0x2 &ipic 22 0x8
423 0xc000 0x0 0x0 0x3 &ipic 23 0x8
424 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
426 interrupts = <66 0x8>;
427 bus-range = <0x0 0x0>;
428 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
429 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
430 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
431 sleep = <&pmc 0x00010000>;
432 clock-frequency = <0>;
436 reg = <0xe0008500 0x100 /* internal registers */
437 0xe0008300 0x8>; /* config space access registers */
448 reg = <0xe0009000 0x00001000>;
449 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
450 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
451 bus-range = <0 255>;
452 interrupt-map-mask = <0xf800 0 0 7>;
453 interrupt-map = <0 0 0 1 &ipic 1 8
454 0 0 0 2 &ipic 1 8
455 0 0 0 3 &ipic 1 8
456 0 0 0 4 &ipic 1 8>;
457 sleep = <&pmc 0x00300000>;
458 clock-frequency = <0>;
460 pcie@0 {
464 reg = <0 0 0 0 0>;
465 ranges = <0x02000000 0 0xa8000000
466 0x02000000 0 0xa8000000
467 0 0x10000000
468 0x01000000 0 0x00000000
469 0x01000000 0 0x00000000
470 0 0x00800000>;
480 reg = <0xe000a000 0x00001000>;
481 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
482 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
483 bus-range = <0 255>;
484 interrupt-map-mask = <0xf800 0 0 7>;
485 interrupt-map = <0 0 0 1 &ipic 2 8
486 0 0 0 2 &ipic 2 8
487 0 0 0 3 &ipic 2 8
488 0 0 0 4 &ipic 2 8>;
489 sleep = <&pmc 0x000c0000>;
490 clock-frequency = <0>;
492 pcie@0 {
496 reg = <0 0 0 0 0>;
497 ranges = <0x02000000 0 0xc8000000
498 0x02000000 0 0xc8000000
499 0 0x10000000
500 0x01000000 0 0x00000000
501 0x01000000 0 0x00000000
502 0 0x00800000>;