Lines Matching +full:0 +full:x98000000
18 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0x00000000>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
48 reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */
54 cell-index = <0>;
55 dcr-reg = <0x0c0 0x009>;
56 #address-cells = <0>;
57 #size-cells = <0>;
65 dcr-reg = <0x0d0 0x009>;
66 #address-cells = <0>;
67 #size-cells = <0>;
69 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
77 dcr-reg = <0x0e0 0x009>;
78 #address-cells = <0>;
79 #size-cells = <0>;
81 interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
90 clock-frequency = <0>; /* Filled in by U-Boot */
94 dcr-reg = <0x010 0x002>;
96 interrupts = <0x5 0x4 /* ECC DED Error */
97 0x6 0x4 /* ECC SEC Error */ >;
102 dcr-reg = <0x180 0x062>;
106 interrupts = <0x0 0x1 0x2 0x3 0x4>;
108 #address-cells = <0>;
109 #size-cells = <0>;
110 interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
111 /*RXEOB*/ 0x1 &UIC0 0xb 0x4
112 /*SERR*/ 0x2 &UIC1 0x0 0x4
113 /*TXDE*/ 0x3 &UIC1 0x1 0x4
114 /*RXDE*/ 0x4 &UIC1 0x2 0x4>;
115 interrupt-map-mask = <0xffffffff>;
122 ranges = <0x80000000 0x80000000 0x10000000
123 0xef600000 0xef600000 0x00a00000
124 0xf0000000 0xf0000000 0x10000000>;
125 dcr-reg = <0x0a0 0x005>;
126 clock-frequency = <0>; /* Filled in by U-Boot */
130 dcr-reg = <0x012 0x002>;
133 clock-frequency = <0>; /* Filled in by U-Boot */
135 interrupts = <0x5 0x1>;
138 nor_flash@0,0 {
141 reg = <0x00000000 0x00000000 0x04000000>;
144 partition@0 {
146 reg = <0x00000000 0x00200000>;
150 reg = <0x00200000 0x00200000>;
154 reg = <0x00400000 0x03b60000>;
158 reg = <0x03f60000 0x00040000>;
162 reg = <0x03fa0000 0x00060000>;
170 reg = <0xef600200 0x00000008>;
171 virtual-reg = <0xef600200>;
172 clock-frequency = <0>; /* Filled in by U-Boot */
173 current-speed = <0>;
175 interrupts = <0x1a 0x4>;
181 reg = <0xef600300 0x00000008>;
182 virtual-reg = <0xef600300>;
183 clock-frequency = <0>; /* Filled in by U-Boot */
184 current-speed = <0>;
186 interrupts = <0x1 0x4>;
191 reg = <0xef600400 0x00000014>;
193 interrupts = <0x2 0x4>;
198 reg = <0xef600500 0x00000014>;
200 interrupts = <0x7 0x4>;
206 reg = <0xef600b00 0x00000104>;
211 linux,network-index = <0x0>;
215 interrupts = <0x0 0x1>;
217 #address-cells = <0>;
218 #size-cells = <0>;
219 interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
220 /*Wake*/ 0x1 &UIC1 0x1d 0x4>;
221 reg = <0xef600900 0x000000c4>;
224 mal-tx-channel = <0>;
225 mal-rx-channel = <0>;
226 cell-index = <0>;
233 phy-map = <0x0000003f>; /* Start at 6 */
235 rgmii-channel = <0>;
241 linux,network-index = <0x1>;
245 interrupts = <0x0 0x1>;
247 #address-cells = <0>;
248 #size-cells = <0>;
249 interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4
250 /*Wake*/ 0x1 &UIC1 0x1f 0x4>;
251 reg = <0xef600a00 0x000000c4>;
263 phy-map = <0x00000000>;
278 port = <0x0>; /* port number */
279 reg = <0xa0000000 0x20000000 /* Config space access */
280 0xef000000 0x00001000>; /* Registers */
281 dcr-reg = <0x040 0x020>;
282 sdr-base = <0x400>;
287 ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000
288 0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>;
290 /* Inbound 2GB range starting at 0 */
291 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
293 /* This drives busses 0x00 to 0x3f */
294 bus-range = <0x0 0x3f>;
302 * The real slot is on idsel 0, so the swizzling is 1:1
304 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
306 0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */
307 0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */
308 0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */
309 0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>;
319 port = <0x1>; /* port number */
320 reg = <0xc0000000 0x20000000 /* Config space access */
321 0xef001000 0x00001000>; /* Registers */
322 dcr-reg = <0x060 0x020>;
323 sdr-base = <0x440>;
328 ranges = <0x02000000 0x00000000 0x80000000 0x98000000 0x00000000 0x08000000
329 0x01000000 0x00000000 0x00000000 0xe0010000 0x00000000 0x00010000>;
331 /* Inbound 2GB range starting at 0 */
332 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
334 /* This drives busses 0x40 to 0x7f */
335 bus-range = <0x40 0x7f>;
343 * The real slot is on idsel 0, so the swizzling is 1:1
345 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
347 0x0 0x0 0x0 0x1 &UIC2 0xb 0x4 /* swizzled int A */
348 0x0 0x0 0x0 0x2 &UIC2 0xc 0x4 /* swizzled int B */
349 0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */
350 0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>;