Lines Matching +full:timebase +full:- +full:frequency

15 /dts-v1/;
18 	#address-cells = <2>;
19 	#size-cells = <1>;
20 	model = "ibm,iss-4xx";
21 	compatible = "ibm,iss-4xx";
22 	dcr-parent = <&{/cpus/cpu@0}>;
29 		#address-cells = <1>;
30 		#size-cells = <0>;
36 			clock-frequency = <100000000>; // 100Mhz :-)
37 			timebase-frequency = <100000000>;
38 			i-cache-line-size = <32>; // may need fixup in sim
39 			d-cache-line-size = <32>; // may need fixup in sim
40 			i-cache-size = <32768>; /* may need fixup in sim */
41 			d-cache-size = <32768>; /* may need fixup in sim */
42 			dcr-controller;
43 			dcr-access-method = "native";
52 	UIC0: interrupt-controller0 {
53 		compatible = "ibm,uic-4xx", "ibm,uic";
54 		interrupt-controller;
55 		cell-index = <0>;
56 		dcr-reg = <0x0c0 0x009>;
57 		#address-cells = <0>;
58 		#size-cells = <0>;
59 		#interrupt-cells = <2>;
63 	UIC1: interrupt-controller1 {
64 		compatible = "ibm,uic-4xx", "ibm,uic";
65 		interrupt-controller;
66 		cell-index = <1>;
67 		dcr-reg = <0x0d0 0x009>;
68 		#address-cells = <0>;
69 		#size-cells = <0>;
70 		#interrupt-cells = <2>;
72 		interrupt-parent = <&UIC0>;
76 		compatible = "ibm,plb-4xx", "ibm,plb4"; /* Could be PLB6, doesn't matter */
77 		#address-cells = <2>;
78 		#size-cells = <1>;
80 		clock-frequency = <0>; // Filled in by zImage
83 			compatible = "ibm,opb-4xx", "ibm,opb";
84 			#address-cells = <1>;
85 			#size-cells = <1>;
86 			/* Wish there was a nicer way of specifying a full 32-bit
90 			clock-frequency = <0>; // Filled in by zImage
95 				virtual-reg = <0xe0000200>;
96 				clock-frequency = <11059200>;
97 				current-speed = <115200>;
98 				interrupt-parent = <&UIC0>;
105 		compatible = "ds1743-nvram", "ds1743", "rtc-ds1743";
108 	iss-block {
109 		compatible = "ibm,iss-sim-block-device";
114 		stdout-path = "/plb/opb/serial@40000200";