Lines Matching +full:soc +full:- +full:level

2  * T1040/T1042 Silicon/SoC Device Tree Source (pre include)
4  * Copyright 2013-2014 Freescale Semiconductor Inc.
35 /dts-v1/;
40 	#address-cells = <2>;
41 	#size-cells = <2>;
42 	interrupt-parent = <&mpic>;
45 		ccsr = &soc;
71 		#address-cells = <1>;
72 		#size-cells = <0>;
78 			next-level-cache = <&L2_1>;
79 			#cooling-cells = <2>;
80 			L2_1: l2-cache {
81 				next-level-cache = <&cpc>;
88 			next-level-cache = <&L2_2>;
89 			#cooling-cells = <2>;
90 			L2_2: l2-cache {
91 				next-level-cache = <&cpc>;
98 			next-level-cache = <&L2_3>;
99 			#cooling-cells = <2>;
100 			L2_3: l2-cache {
101 				next-level-cache = <&cpc>;
108 			next-level-cache = <&L2_4>;
109 			#cooling-cells = <2>;
110 			L2_4: l2-cache {
111 				next-level-cache = <&cpc>;