Lines Matching +full:soc +full:- +full:level

2  * P3041 Silicon/SoC Device Tree Source (pre include)
4  * Copyright 2011 - 2015 Freescale Semiconductor Inc.
35 /dts-v1/;
41 	#address-cells = <2>;
42 	#size-cells = <2>;
43 	interrupt-parent = <&mpic>;
46 		ccsr = &soc;
87 		#address-cells = <1>;
88 		#size-cells = <0>;
94 			next-level-cache = <&L2_0>;
95 			fsl,portid-mapping = <0x80000000>;
96 			L2_0: l2-cache {
97 				next-level-cache = <&cpc>;
104 			next-level-cache = <&L2_1>;
105 			fsl,portid-mapping = <0x40000000>;
106 			L2_1: l2-cache {
107 				next-level-cache = <&cpc>;
114 			next-level-cache = <&L2_2>;
115 			fsl,portid-mapping = <0x20000000>;
116 			L2_2: l2-cache {
117 				next-level-cache = <&cpc>;
124 			next-level-cache = <&L2_3>;
125 			fsl,portid-mapping = <0x10000000>;
126 			L2_3: l2-cache {
127 				next-level-cache = <&cpc>;