Lines Matching +full:soc +full:- +full:level

2  * P2041 Silicon/SoC Device Tree Source (pre include)
4  * Copyright 2011 - 2015 Freescale Semiconductor Inc.
35 /dts-v1/;
41 	#address-cells = <2>;
42 	#size-cells = <2>;
43 	interrupt-parent = <&mpic>;
46 		ccsr = &soc;
86 		#address-cells = <1>;
87 		#size-cells = <0>;
93 			next-level-cache = <&L2_0>;
94 			fsl,portid-mapping = <0x80000000>;
95 			L2_0: l2-cache {
96 				next-level-cache = <&cpc>;
103 			next-level-cache = <&L2_1>;
104 			fsl,portid-mapping = <0x40000000>;
105 			L2_1: l2-cache {
106 				next-level-cache = <&cpc>;
113 			next-level-cache = <&L2_2>;
114 			fsl,portid-mapping = <0x20000000>;
115 			L2_2: l2-cache {
116 				next-level-cache = <&cpc>;
123 			next-level-cache = <&L2_3>;
124 			fsl,portid-mapping = <0x10000000>;
125 			L2_3: l2-cache {
126 				next-level-cache = <&cpc>;