Lines Matching +full:0 +full:x8800
18 reg = <0x0 0x00000000 0x0 0x40000000>; // 1G at 0x0
22 reg = <0x0f 0xffe05000 0x0 0x1000>;
24 ranges = <0 0 0xf 0xef800000 0x00800000
25 2 0 0xf 0xffdf8000 0x00008000
26 3 0 0xf 0xffdf0000 0x00008000>;
28 flash@0,0 {
30 reg = <0 0 0x00800000>;
35 partition@0 {
37 reg = <0x00000000 0x00300000>;
41 reg = <0x00300000 0x00100000>;
46 reg = <0x00400000 0x00300000>;
50 reg = <0x00700000 0x00100000>;
57 ranges = <0x00000000 0x0f 0xffe00000 0x00100000>;
66 phy0: ethernet-phy@0 {
67 interrupts = <10 1 0 0>;
68 reg = <0>;
71 interrupts = <10 1 0 0>;
75 interrupts = <10 1 0 0>;
79 interrupts = <10 1 0 0>;
83 reg = <0x11>;
96 reg = <0x11>;
109 reg = <0x11>;
122 reg = <0x11>;
129 reg = <0x0f 0xffe08000 0x0 0x1000>;
130 ranges = <0x02000000 0x0 0xe0000000 0x0c 0x00000000 0x0 0x20000000
131 0x01000000 0x0 0x00000000 0x0f 0xffc00000 0x0 0x00010000>;
132 interrupt-map-mask = <0xff00 0 0 7>;
134 /* IDSEL 0x11 func 0 - PCI slot 1 */
135 0x8800 0 0 1 &mpic 2 1 0 0
136 0x8800 0 0 2 &mpic 3 1 0 0
137 0x8800 0 0 3 &mpic 4 1 0 0
138 0x8800 0 0 4 &mpic 1 1 0 0
140 /* IDSEL 0x11 func 1 - PCI slot 1 */
141 0x8900 0 0 1 &mpic 2 1 0 0
142 0x8900 0 0 2 &mpic 3 1 0 0
143 0x8900 0 0 3 &mpic 4 1 0 0
144 0x8900 0 0 4 &mpic 1 1 0 0
146 /* IDSEL 0x11 func 2 - PCI slot 1 */
147 0x8a00 0 0 1 &mpic 2 1 0 0
148 0x8a00 0 0 2 &mpic 3 1 0 0
149 0x8a00 0 0 3 &mpic 4 1 0 0
150 0x8a00 0 0 4 &mpic 1 1 0 0
152 /* IDSEL 0x11 func 3 - PCI slot 1 */
153 0x8b00 0 0 1 &mpic 2 1 0 0
154 0x8b00 0 0 2 &mpic 3 1 0 0
155 0x8b00 0 0 3 &mpic 4 1 0 0
156 0x8b00 0 0 4 &mpic 1 1 0 0
158 /* IDSEL 0x11 func 4 - PCI slot 1 */
159 0x8c00 0 0 1 &mpic 2 1 0 0
160 0x8c00 0 0 2 &mpic 3 1 0 0
161 0x8c00 0 0 3 &mpic 4 1 0 0
162 0x8c00 0 0 4 &mpic 1 1 0 0
164 /* IDSEL 0x11 func 5 - PCI slot 1 */
165 0x8d00 0 0 1 &mpic 2 1 0 0
166 0x8d00 0 0 2 &mpic 3 1 0 0
167 0x8d00 0 0 3 &mpic 4 1 0 0
168 0x8d00 0 0 4 &mpic 1 1 0 0
170 /* IDSEL 0x11 func 6 - PCI slot 1 */
171 0x8e00 0 0 1 &mpic 2 1 0 0
172 0x8e00 0 0 2 &mpic 3 1 0 0
173 0x8e00 0 0 3 &mpic 4 1 0 0
174 0x8e00 0 0 4 &mpic 1 1 0 0
176 /* IDSEL 0x11 func 7 - PCI slot 1 */
177 0x8f00 0 0 1 &mpic 2 1 0 0
178 0x8f00 0 0 2 &mpic 3 1 0 0
179 0x8f00 0 0 3 &mpic 4 1 0 0
180 0x8f00 0 0 4 &mpic 1 1 0 0
182 /* IDSEL 0x12 func 0 - PCI slot 2 */
183 0x9000 0 0 1 &mpic 3 1 0 0
184 0x9000 0 0 2 &mpic 4 1 0 0
185 0x9000 0 0 3 &mpic 1 1 0 0
186 0x9000 0 0 4 &mpic 2 1 0 0
188 /* IDSEL 0x12 func 1 - PCI slot 2 */
189 0x9100 0 0 1 &mpic 3 1 0 0
190 0x9100 0 0 2 &mpic 4 1 0 0
191 0x9100 0 0 3 &mpic 1 1 0 0
192 0x9100 0 0 4 &mpic 2 1 0 0
194 /* IDSEL 0x12 func 2 - PCI slot 2 */
195 0x9200 0 0 1 &mpic 3 1 0 0
196 0x9200 0 0 2 &mpic 4 1 0 0
197 0x9200 0 0 3 &mpic 1 1 0 0
198 0x9200 0 0 4 &mpic 2 1 0 0
200 /* IDSEL 0x12 func 3 - PCI slot 2 */
201 0x9300 0 0 1 &mpic 3 1 0 0
202 0x9300 0 0 2 &mpic 4 1 0 0
203 0x9300 0 0 3 &mpic 1 1 0 0
204 0x9300 0 0 4 &mpic 2 1 0 0
206 /* IDSEL 0x12 func 4 - PCI slot 2 */
207 0x9400 0 0 1 &mpic 3 1 0 0
208 0x9400 0 0 2 &mpic 4 1 0 0
209 0x9400 0 0 3 &mpic 1 1 0 0
210 0x9400 0 0 4 &mpic 2 1 0 0
212 /* IDSEL 0x12 func 5 - PCI slot 2 */
213 0x9500 0 0 1 &mpic 3 1 0 0
214 0x9500 0 0 2 &mpic 4 1 0 0
215 0x9500 0 0 3 &mpic 1 1 0 0
216 0x9500 0 0 4 &mpic 2 1 0 0
218 /* IDSEL 0x12 func 6 - PCI slot 2 */
219 0x9600 0 0 1 &mpic 3 1 0 0
220 0x9600 0 0 2 &mpic 4 1 0 0
221 0x9600 0 0 3 &mpic 1 1 0 0
222 0x9600 0 0 4 &mpic 2 1 0 0
224 /* IDSEL 0x12 func 7 - PCI slot 2 */
225 0x9700 0 0 1 &mpic 3 1 0 0
226 0x9700 0 0 2 &mpic 4 1 0 0
227 0x9700 0 0 3 &mpic 1 1 0 0
228 0x9700 0 0 4 &mpic 2 1 0 0
230 // IDSEL 0x1c USB
231 0xe000 0 0 1 &i8259 12 2
232 0xe100 0 0 2 &i8259 9 2
233 0xe200 0 0 3 &i8259 10 2
234 0xe300 0 0 4 &i8259 11 2
236 // IDSEL 0x1d Audio
237 0xe800 0 0 1 &i8259 6 2
239 // IDSEL 0x1e Legacy
240 0xf000 0 0 1 &i8259 7 2
241 0xf100 0 0 1 &i8259 7 2
243 // IDSEL 0x1f IDE/SATA
244 0xf800 0 0 1 &i8259 14 2
245 0xf900 0 0 1 &i8259 5 2
248 pcie@0 {
249 ranges = <0x02000000 0x0 0xe0000000
250 0x02000000 0x0 0xe0000000
251 0x0 0x20000000
253 0x01000000 0x0 0x00000000
254 0x01000000 0x0 0x00000000
255 0x0 0x00010000>;
256 uli1575@0 {
257 reg = <0 0 0 0 0>;
260 ranges = <0x02000000 0x0 0xe0000000
261 0x02000000 0x0 0xe0000000
262 0x0 0x20000000
263 0x01000000 0x0 0x00000000
264 0x01000000 0x0 0x00000000
265 0x0 0x00010000>;
270 reg = <0xf000 0 0 0 0>;
271 ranges = <1 0 0x01000000 0 0
272 0x00001000>;
276 reg = <1 0x20 2
277 1 0xa0 2
278 1 0x4d0 2>;
281 #address-cells = <0>;
284 interrupts = <9 2 0 0>;
288 #size-cells = <0>;
290 reg = <1 0x60 1 1 0x64 1>;
294 keyboard@0 {
295 reg = <0>;
308 reg = <1 0x70 2>;
312 reg = <1 0x400 0x80>;
321 reg = <0x0f 0xffe09000 0x0 0x1000>;
322 ranges = <0x02000000 0x0 0xe0000000 0x0c 0x20000000 0x0 0x20000000
323 0x01000000 0x0 0x00000000 0x0f 0xffc10000 0x0 0x00010000>;
325 pcie@0 {
326 ranges = <0x02000000 0x0 0xe0000000
327 0x02000000 0x0 0xe0000000
328 0x0 0x20000000
330 0x01000000 0x0 0x00000000
331 0x01000000 0x0 0x00000000
332 0x0 0x00010000>;