Lines Matching +full:0 +full:x2800
36 nor@0,0 {
40 reg = <0x0 0x0 0x01000000>;
44 partition@0 {
45 reg = <0x0 0x0b00000>;
50 reg = <0x0b00000 0x0400000>;
55 reg = <0x0f00000 0x060000>;
60 reg = <0x0f60000 0x020000>;
66 reg = <0x0f80000 0x080000>;
72 board-control@1,0 {
74 reg = <0x1 0x0 0x1000>;
82 reg = <0x50>;
87 reg = <0x56>;
92 reg = <0x57>;
99 reg = <0x50>;
109 phy0: ethernet-phy@0 {
110 interrupts = <5 1 0 0>;
111 reg = <0x0>;
114 interrupts = <5 1 0 0>;
115 reg = <0x1>;
118 interrupts = <5 1 0 0>;
119 reg = <0x2>;
122 interrupts = <5 1 0 0>;
123 reg = <0x3>;
126 reg = <0x11>;
138 reg = <0x11>;
150 reg = <0x11>;
162 reg = <0x11>;
169 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
171 /* IDSEL 0x4 (PCIX Slot 2) */
172 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
173 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
174 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
175 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
177 /* IDSEL 0x5 (PCIX Slot 3) */
178 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
179 0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
180 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
181 0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
183 /* IDSEL 0x6 (PCIX Slot 4) */
184 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
185 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
186 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
187 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
189 /* IDSEL 0x8 (PCIX Slot 5) */
190 0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
191 0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
192 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
193 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
195 /* IDSEL 0xC (Tsi310 bridge) */
196 0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
197 0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
198 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
199 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
201 /* IDSEL 0x14 (Slot 2) */
202 0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
203 0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
204 0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
205 0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
207 /* IDSEL 0x15 (Slot 3) */
208 0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
209 0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
210 0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
211 0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
213 /* IDSEL 0x16 (Slot 4) */
214 0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
215 0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
216 0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
217 0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
219 /* IDSEL 0x18 (Slot 5) */
220 0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
221 0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
222 0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
223 0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
225 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
226 0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
227 0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
228 0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
229 0xe000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
232 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
235 /* IDSEL 0x00 (PrPMC Site) */
236 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
237 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
238 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
239 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
241 /* IDSEL 0x04 (VIA chip) */
242 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
243 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
244 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
245 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
247 /* IDSEL 0x05 (8139) */
248 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
250 /* IDSEL 0x06 (Slot 6) */
251 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
252 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
253 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
254 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
256 /* IDESL 0x07 (Slot 7) */
257 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
258 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 0 0
259 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
260 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1 0 0>;
262 reg = <0xe000 0x0 0x0 0x0 0x0>;
266 ranges = <0x2000000 0x0 0x80000000
267 0x2000000 0x0 0x80000000
268 0x0 0x20000000
269 0x1000000 0x0 0x0
270 0x1000000 0x0 0x0
271 0x0 0x80000>;
279 reg = <0x2000 0x0 0x0 0x0 0x0>;
280 ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
286 reg = <0x1 0x20 0x2
287 0x1 0xa0 0x2
288 0x1 0x4d0 0x2>;
289 #address-cells = <0>;
292 interrupts = <0 1 0 0>;
298 reg = <0x1 0x70 0x2>;