376 	unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0;  in handle_unaligned()
393 				regs->iaoq[0], regs->iir);  in handle_unaligned()
404 	switch (MAJOR_OP(regs->iir))  in handle_unaligned()
409 		if (regs->iir&0x20)  in handle_unaligned()
412 			if (regs->iir&0x1000)		/* short loads */  in handle_unaligned()
413 				if (regs->iir&0x200)  in handle_unaligned()
414 					newbase += IM5_3(regs->iir);  in handle_unaligned()
416 					newbase += IM5_2(regs->iir);  in handle_unaligned()
417 			else if (regs->iir&0x2000)	/* scaled indexed */  in handle_unaligned()
420 				switch (regs->iir & OPCODE1_MASK)  in handle_unaligned()
430 				newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0)<<shift;  in handle_unaligned()
432 				newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0);  in handle_unaligned()
438 		newbase += IM14(regs->iir);  in handle_unaligned()
442 		if (regs->iir&8)  in handle_unaligned()
445 			newbase += IM14(regs->iir&~0xe);  in handle_unaligned()
451 		newbase += IM14(regs->iir&6);  in handle_unaligned()
455 		if (regs->iir&4)  in handle_unaligned()
458 			newbase += IM14(regs->iir&~4);  in handle_unaligned()
464 	switch (regs->iir & OPCODE1_MASK)  in handle_unaligned()
468 		ret = emulate_ldh(regs, R3(regs->iir));  in handle_unaligned()
475 		ret = emulate_ldw(regs, R3(regs->iir),0);  in handle_unaligned()
479 		ret = emulate_sth(regs, R2(regs->iir));  in handle_unaligned()
484 		ret = emulate_stw(regs, R2(regs->iir),0);  in handle_unaligned()
492 		ret = emulate_ldd(regs, R3(regs->iir),0);  in handle_unaligned()
497 		ret = emulate_std(regs, R2(regs->iir),0);  in handle_unaligned()
505 		ret = emulate_ldw(regs,FR3(regs->iir),1);  in handle_unaligned()
510 		ret = emulate_ldd(regs,R3(regs->iir),1);  in handle_unaligned()
517 		ret = emulate_stw(regs,FR3(regs->iir),1);  in handle_unaligned()
522 		ret = emulate_std(regs,R3(regs->iir),1);  in handle_unaligned()
532 	switch (regs->iir & OPCODE2_MASK)  in handle_unaligned()
535 		ret = emulate_ldd(regs,R2(regs->iir),1);  in handle_unaligned()
538 		ret = emulate_std(regs, R2(regs->iir),1);  in handle_unaligned()
542 		ret = emulate_ldd(regs, R2(regs->iir),0);  in handle_unaligned()
545 		ret = emulate_std(regs, R2(regs->iir),0);  in handle_unaligned()
549 	switch (regs->iir & OPCODE3_MASK)  in handle_unaligned()
552 		ret = emulate_ldw(regs, R2(regs->iir), 1);  in handle_unaligned()
555 		ret = emulate_ldw(regs, R2(regs->iir), 0);  in handle_unaligned()
559 		ret = emulate_stw(regs, R2(regs->iir),1);  in handle_unaligned()
562 		ret = emulate_stw(regs, R2(regs->iir),0);  in handle_unaligned()
565 	switch (regs->iir & OPCODE4_MASK)  in handle_unaligned()
568 		ret = emulate_ldh(regs, R2(regs->iir));  in handle_unaligned()
572 		ret = emulate_ldw(regs, R2(regs->iir),0);  in handle_unaligned()
575 		ret = emulate_sth(regs, R2(regs->iir));  in handle_unaligned()
579 		ret = emulate_stw(regs, R2(regs->iir),0);  in handle_unaligned()
583 	if (ret == 0 && modify && R1(regs->iir))  in handle_unaligned()
584 		regs->gr[R1(regs->iir)] = newbase;  in handle_unaligned()
588 		printk(KERN_CRIT "Not-handled unaligned insn 0x%08lx\n", regs->iir);  in handle_unaligned()
638 	switch (regs->iir & OPCODE1_MASK) {  in check_unaligned()
656 		switch (regs->iir & OPCODE4_MASK) {  in check_unaligned()