Lines Matching +full:32 +full:mb
26 /* Frame alignment for 32- and 64-bit */
62 #define LDREGM ldd,mb
138 zdep \r, 31-(\sa), 32-(\sa), \t
146 /* Shift Right for 32-bit. Clobbers upper 32-bit on PA2.0. */
148 extru \r, 31-(\sa), 32-(\sa), \t
156 /* Extract unsigned for 32- and 64-bit
157 * The extru instruction leaves the most significant 32 bits of the
161 extrd,u \r, 32+(\p), \len, \t
167 /* The depi instruction leaves the most significant 32 bits of the
171 depdi \i, 32+(\p), \len, \t
177 /* The depw instruction leaves the most significant 32 bits of the
181 depd \i, 32+(\p), \len, \t
187 /* load 32-bit 'value' into 'reg' compensating for the ldil
316 fldd,mb -8(\regs), %fr30
317 fldd,mb -8(\regs), %fr29
318 fldd,mb -8(\regs), %fr28
319 fldd,mb -8(\regs), %fr27
320 fldd,mb -8(\regs), %fr26
321 fldd,mb -8(\regs), %fr25
322 fldd,mb -8(\regs), %fr24
323 fldd,mb -8(\regs), %fr23
324 fldd,mb -8(\regs), %fr22
325 fldd,mb -8(\regs), %fr21
326 fldd,mb -8(\regs), %fr20
327 fldd,mb -8(\regs), %fr19
328 fldd,mb -8(\regs), %fr18
329 fldd,mb -8(\regs), %fr17
330 fldd,mb -8(\regs), %fr16
331 fldd,mb -8(\regs), %fr15
332 fldd,mb -8(\regs), %fr14
333 fldd,mb -8(\regs), %fr13
334 fldd,mb -8(\regs), %fr12
335 fldd,mb -8(\regs), %fr11
336 fldd,mb -8(\regs), %fr10
337 fldd,mb -8(\regs), %fr9
338 fldd,mb -8(\regs), %fr8
339 fldd,mb -8(\regs), %fr7
340 fldd,mb -8(\regs), %fr6
341 fldd,mb -8(\regs), %fr5
342 fldd,mb -8(\regs), %fr4
343 fldd,mb -8(\regs), %fr3
344 fldd,mb -8(\regs), %fr2
345 fldd,mb -8(\regs), %fr1
346 fldd,mb -8(\regs), %fr0
363 fldd,mb -8(%r30), %fr21
364 fldd,mb -8(%r30), %fr20
365 fldd,mb -8(%r30), %fr19
366 fldd,mb -8(%r30), %fr18
367 fldd,mb -8(%r30), %fr17
368 fldd,mb -8(%r30), %fr16
369 fldd,mb -8(%r30), %fr15
370 fldd,mb -8(%r30), %fr14
371 fldd,mb -8(%r30), %fr13
372 fldd,mb -8(%r30), %fr12
392 std %r17, -32(%r30)
400 ldd -32(%r30), %r17
415 ldd,mb -CALLEE_REG_FRAME_SIZE(%r30), %r3
459 ldw,mb -CALLEE_REG_FRAME_SIZE(%r30), %r3