Lines Matching +full:sw +full:- +full:reset +full:- +full:number
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
26 #include <asm/asm-offsets.h>
30 l.movhi rd,hi(-KERNELBASE) ;\
73 #define EMERGENCY_PRINT_STORE_GPR4 l.sw 0x20(r0),r4
76 #define EMERGENCY_PRINT_STORE_GPR5 l.sw 0x24(r0),r5
79 #define EMERGENCY_PRINT_STORE_GPR6 l.sw 0x28(r0),r6
82 #define EMERGENCY_PRINT_STORE_GPR7 l.sw 0x2c(r0),r7
85 #define EMERGENCY_PRINT_STORE_GPR8 l.sw 0x30(r0),r8
88 #define EMERGENCY_PRINT_STORE_GPR9 l.sw 0x34(r0),r9
113 #define EXCEPTION_STORE_GPR2 l.sw 0x64(r0),r2
116 #define EXCEPTION_STORE_GPR3 l.sw 0x68(r0),r3
119 #define EXCEPTION_STORE_GPR4 l.sw 0x6c(r0),r4
122 #define EXCEPTION_STORE_GPR5 l.sw 0x70(r0),r5
125 #define EXCEPTION_STORE_GPR6 l.sw 0x74(r0),r6
145 #define EXCEPTION_T_STORE_GPR30 l.sw 0x78(r0),r30
148 #define EXCEPTION_T_STORE_GPR10 l.sw 0x7c(r0),r10
151 #define EXCEPTION_T_STORE_SP l.sw 0x80(r0),r1
172 /* Load r10 from current_thread_info_set - clobbers r1 and r30 */
195 * PRMS: handler - a function to jump to. it has to save the
197 * appropriate arch-independant exception handler
205 * r1 - ksp pointing to the new (exception) frame
206 * r4 - EEAR exception EA
207 * r10 - current pointing to current_thread_info struct
208 * r12 - syscall 0, since we didn't come from syscall
209 * r30 - handler address of the handler we'll jump to
238 l.addi r1,r1,-(INT_FRAME_SIZE) ;\
241 l.sw PT_GPR12(r30),r12 ;\
244 l.sw PT_PC(r30),r12 ;\
246 l.sw PT_SR(r30),r12 ;\
249 l.sw PT_GPR30(r30),r12 ;\
252 l.sw PT_GPR10(r30),r12 ;\
255 l.sw PT_SP(r30),r12 ;\
257 l.sw PT_GPR4(r30),r4 ;\
261 /* ----- turn on MMU ----- */ ;\
326 l.addi r1,r1,-(INT_FRAME_SIZE) ;\
329 l.sw PT_GPR12(r30),r12 ;\
331 l.sw PT_PC(r30),r12 ;\
333 l.sw PT_SR(r30),r12 ;\
336 l.sw PT_GPR30(r30),r12 ;\
339 l.sw PT_GPR10(r30),r12 ;\
342 l.sw PT_SP(r30),r12 ;\
343 l.sw PT_GPR13(r30),r13 ;\
344 /* --> */ ;\
346 l.sw PT_GPR4(r30),r4 ;\
350 /* ----- play a MMU trick ----- */ ;\
360 /* ---[ 0x100: RESET exception ]----------------------------------------- */
370 /* ---[ 0x200: BUS exception ]------------------------------------------- */
375 /* ---[ 0x300: Data Page Fault exception ]------------------------------- */
384 /* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
393 /* ---[ 0x500: Timer exception ]----------------------------------------- */
397 /* ---[ 0x600: Alignment exception ]-------------------------------------- */
401 /* ---[ 0x700: Illegal insn exception ]---------------------------------- */
405 /* ---[ 0x800: External interrupt exception ]---------------------------- */
409 /* ---[ 0x900: DTLB miss exception ]------------------------------------- */
414 /* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
419 /* ---[ 0xb00: Range exception ]----------------------------------------- */
423 /* ---[ 0xc00: Syscall exception ]--------------------------------------- */
427 /* ---[ 0xd00: Trap exception ]------------------------------------------ */
431 /* ---[ 0xe00: Trap exception ]------------------------------------------ */
436 /* ---[ 0xf00: Reserved exception ]-------------------------------------- */
440 /* ---[ 0x1000: Reserved exception ]------------------------------------- */
444 /* ---[ 0x1100: Reserved exception ]------------------------------------- */
448 /* ---[ 0x1200: Reserved exception ]------------------------------------- */
452 /* ---[ 0x1300: Reserved exception ]------------------------------------- */
456 /* ---[ 0x1400: Reserved exception ]------------------------------------- */
460 /* ---[ 0x1500: Reserved exception ]------------------------------------- */
464 /* ---[ 0x1600: Reserved exception ]------------------------------------- */
468 /* ---[ 0x1700: Reserved exception ]------------------------------------- */
472 /* ---[ 0x1800: Reserved exception ]------------------------------------- */
476 /* ---[ 0x1900: Reserved exception ]------------------------------------- */
480 /* ---[ 0x1a00: Reserved exception ]------------------------------------- */
484 /* ---[ 0x1b00: Reserved exception ]------------------------------------- */
488 /* ---[ 0x1c00: Reserved exception ]------------------------------------- */
492 /* ---[ 0x1d00: Reserved exception ]------------------------------------- */
496 /* ---[ 0x1e00: Reserved exception ]------------------------------------- */
500 /* ---[ 0x1f00: Reserved exception ]------------------------------------- */
581 l.sw TI_KSP(r31), r1
588 * .bss contains uninitialized data - clear it up
598 l.sw (0)(r28),r0
644 // reset the simulation counters
654 /* magic number mismatch, set fdt pointer to null */
711 l.addi r7,r0,128 /* Maximum number of sets */
720 l.addi r7,r7,-1
756 /* Wakeup - Restore exception handler */
761 * Check if we actually got the release signal, if not go-back to
782 l.sw TI_KSP(r30),r1
836 l.addi r5,r0,-1
852 /* Establish number of cache sets
853 r16 contains number of cache sets
902 l.addi r5,r0,-1
918 /* Establish number of cache sets
919 r16 contains number of cache sets
956 /* ---[ boot dtlb miss handler ]----------------------------------------- */
960 /* mask for DTLB_MR register: - (0) sets V (valid) bit,
961 * - (31-12) sets bits belonging to VPN (31-12)
965 /* mask for DTLB_TR register: - (2) sets CI (cache inhibit) bit,
966 * - (4) sets A (access) bit,
967 * - (5) sets D (dirty) bit,
968 * - (8) sets SRE (superuser read) bit
969 * - (9) sets SWE (superuser write) bit
970 * - (31-12) sets bits belonging to VPN (31-12)
985 l.sfeqi r6,0 // r6 == 0x1 --> SM
1005 …l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VPN…
1011 l.sll r5, r5, r6 // r5 = number DMMU sets
1012 l.addi r6, r5, -1 // r6 = nsets mask
1013 l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK
1015 l.or r6,r6,r4 // r6 <- r4
1016 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1017 l.movhi r5,hi(DTLB_MR_MASK) // r5 <- ffff:0000.x000
1018 l.ori r5,r5,lo(DTLB_MR_MASK) // r5 <- ffff:1111.x001 - apply DTLB_MR_MASK
1019 l.and r5,r5,r6 // r5 <- VPN :VPN .x001 - we have DTLBMR entry
1026 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
1028 tophys(r3,r4) // r3 <- PA
1030 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1031 l.movhi r5,hi(DTLB_TR_MASK) // r5 <- ffff:0000.x000
1032 l.ori r5,r5,lo(DTLB_TR_MASK) // r5 <- ffff:1111.x330 - apply DTLB_MR_MASK
1033 l.and r5,r5,r3 // r5 <- PPN :PPN .x330 - we have DTLBTR entry
1042 l.rfe // SR <- ESR, PC <- EPC
1050 /* ---[ boot itlb miss handler ]----------------------------------------- */
1054 /* mask for ITLB_MR register: - sets V (valid) bit,
1055 * - sets bits belonging to VPN (15-12)
1059 /* mask for ITLB_TR register: - sets A (access) bit,
1060 * - sets SXE (superuser execute) bit
1061 * - sets bits belonging to VPN (15-12)
1081 l.sfeqi r6,0 // r6 == 0x1 --> SM
1092 …l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VP…
1098 l.sll r5, r5, r6 // r5 = number IMMU sets from IMMUCFGR
1099 l.addi r6, r5, -1 // r6 = nsets mask
1100 l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK
1102 l.or r6,r6,r4 // r6 <- r4
1103 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1104 l.movhi r5,hi(ITLB_MR_MASK) // r5 <- ffff:0000.x000
1105 l.ori r5,r5,lo(ITLB_MR_MASK) // r5 <- ffff:1111.x001 - apply ITLB_MR_MASK
1106 l.and r5,r5,r6 // r5 <- VPN :VPN .x001 - we have ITLBMR entry
1119 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
1121 tophys(r3,r4) // r3 <- PA
1123 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1124 l.movhi r5,hi(ITLB_TR_MASK) // r5 <- ffff:0000.x000
1125 l.ori r5,r5,lo(ITLB_TR_MASK) // r5 <- ffff:1111.x050 - apply ITLB_MR_MASK
1126 l.and r5,r5,r3 // r5 <- PPN :PPN .x050 - we have ITLBTR entry
1135 l.rfe // SR <- ESR, PC <- EPC
1171 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
1191 l.andi r3,r2,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
1206 // Determine number of DMMU sets
1211 l.sll r3, r3, r2 // r3 = number DMMU sets DMMUCFGR
1212 l.addi r2, r3, -1 // r2 = nsets mask
1215 l.and r2, r3, r2 // calc offset: & (NUM_TLB_ENTRIES-1)
1251 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
1272 l.andi r3,r2,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
1291 // Determine number of IMMU sets
1296 l.sll r3, r3, r2 // r3 = number IMMU sets IMMUCFGR
1297 l.addi r2, r3, -1 // r2 = nsets mask
1300 l.and r2, r3, r2 // calc offset: & (NUM_TLB_ENTRIES-1)
1340 * PRMS: r7 - a 32-bit value with an ASCII character in the first byte
1346 * r4 - to store UART_BASE_ADD
1347 * r5 - for loading OFF_TXFULL / THRE,TEMT
1348 * r6 - for storing bitmask (SERIAL_8250)
1368 l.sw 0(r4),r7
1398 * PRMS: r3 - address of the first character of null
1429 * DSCR: prints a number in r3 in hex.
1431 * PRMS: r3 - a 32-bit unsigned integer
1445 l.addi r8,r8,-0x4
1449 /* don't skip the last zero if number == 0x0 */
1465 /* Numbers greater than 9 translate to a-f */
1477 l.addi r8,r8,-0x4