Lines Matching full:have
80 bool "Have write through data caches"
97 bool "Have instruction l.ff1"
103 bool "Have instruction l.fl1"
109 bool "Have instruction l.mul for hardware multiply"
115 bool "Have instruction l.div for hardware divide"
121 bool "Have instruction l.cmov for conditional move"
134 bool "Have instruction l.ror for rotate right"
147 bool "Have instruction l.rori for rotate right with immediate"
160 bool "Have instructions l.ext* for sign extension"
183 This enables support for systems with more than one CPU. If you have
184 a system with only one CPU, say N. If you have a system with more
198 OpenRISC architecture makes it optional to have it implemented
199 in hardware and the OR1200 does not have it.
231 your kernel crashes this doesn't have any influence.