1 // SPDX-License-Identifier: GPL-2.0-only
5  *  Copyright (C) 2007-2013 Bruce Chang (Mediatek)
6  *  Copyright (C) 2013-2016 John Crispin <john@phrozen.org>
21 #include <asm/mach-ralink/ralink_regs.h>
22 #include <asm/mach-ralink/mt7620.h>
121 			pr_warn("PCIE-PHY retry failed.\n");  in wait_pciephy_busy()
122 			return -1;  in wait_pciephy_busy()
140 	unsigned int slot = PCI_SLOT(devfn);  in pci_config_read()  local
147 		num = bus->number;  in pci_config_read()
149 	address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) |  in pci_config_read()
172 	unsigned int slot = PCI_SLOT(devfn);  in pci_config_write()  local
179 		num = bus->number;  in pci_config_write()
181 	address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) |  in pci_config_write()
223 	/* bypass PCIe DLL */  in mt7620_pci_hw_init()
244 		dev_err(&pdev->dev, "pcie PLL not locked, aborting init\n");  in mt7620_pci_hw_init()
247 		return -1;  in mt7620_pci_hw_init()
278 	dev_err(&pdev->dev, "Port 0 N_FTS = %x\n", (unsigned int) val);  in mt7628_pci_hw_init()
291 	rstpcie0 = devm_reset_control_get_exclusive(&pdev->dev, "pcie0");  in mt7620_pci_probe()
295 	bridge_base = devm_ioremap_resource(&pdev->dev, bridge_res);  in mt7620_pci_probe()
299 	pcie_base = devm_ioremap_resource(&pdev->dev, pcie_res);  in mt7620_pci_probe()
312 			return -1;  in mt7620_pci_probe()
318 			return -1;  in mt7620_pci_probe()
322 		dev_err(&pdev->dev, "pcie is not supported on this hardware\n");  in mt7620_pci_probe()
323 		return -1;  in mt7620_pci_probe()
337 		dev_err(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n");  in mt7620_pci_probe()
338 		return -1;  in mt7620_pci_probe()
356 	pci_load_of_ranges(&mt7620_controller, pdev->dev.of_node);  in mt7620_pci_probe()
362 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)  in pcibios_map_irq()  argument
368 	if ((dev->bus->number == 0) && (slot == 0)) {  in pcibios_map_irq()
370 		pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4,  in pcibios_map_irq()
372 		pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val);  in pcibios_map_irq()
373 	} else if ((dev->bus->number == 1) && (slot == 0x0)) {  in pcibios_map_irq()
376 		dev_err(&dev->dev, "no irq found - bus=0x%x, slot = 0x%x\n",  in pcibios_map_irq()
377 			dev->bus->number, slot);  in pcibios_map_irq()
380 	dev_err(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n",  in pcibios_map_irq()
381 		dev->bus->number, slot, irq);  in pcibios_map_irq()
390 	/* setup the slot */  in pcibios_map_irq()
393 	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);  in pcibios_map_irq()
404 	{ .compatible = "mediatek,mt7620-pci" },
411 		.name = "mt7620-pci",