1 // SPDX-License-Identifier: GPL-2.0-only
4  *  Copyright (C) 2011-2012 John Crispin <john@phrozen.org>
5  *  Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
125 #define PMU1_PCIE_PHY	BIT(0)	/* vr9-specific,moved in ar10/grx390 */
166 	do {} while (--retry && (pmu_r32(PMU_PWDSR) & module));  in ltq_pmu_enable()
181 	do {} while (--retry && (!(pmu_r32(PMU_PWDSR) & module)));  in ltq_pmu_disable()
192 	ltq_cgu_w32(ltq_cgu_r32(ifccr) | clk->bits, ifccr);  in cgu_enable()
199 	ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~clk->bits, ifccr);  in cgu_disable()
209 		pmu_w32(clk->bits, PWDCR_EN_XRX(clk->module));  in pmu_enable()
210 		do {} while (--retry &&  in pmu_enable()
211 			     (!(pmu_r32(PWDSR_XRX(clk->module)) & clk->bits)));  in pmu_enable()
215 		pmu_w32(pmu_r32(PWDCR(clk->module)) & ~clk->bits,  in pmu_enable()
216 				PWDCR(clk->module));  in pmu_enable()
217 		do {} while (--retry &&  in pmu_enable()
218 			     (pmu_r32(PWDSR(clk->module)) & clk->bits));  in pmu_enable()
235 		pmu_w32(clk->bits, PWDCR_DIS_XRX(clk->module));  in pmu_disable()
236 		do {} while (--retry &&  in pmu_disable()
237 			     (pmu_r32(PWDSR_XRX(clk->module)) & clk->bits));  in pmu_disable()
240 		pmu_w32(pmu_r32(PWDCR(clk->module)) | clk->bits,  in pmu_disable()
241 				PWDCR(clk->module));  in pmu_disable()
242 		do {} while (--retry &&  in pmu_disable()
243 			     (!(pmu_r32(PWDSR(clk->module)) & clk->bits)));  in pmu_disable()
259 		if (clk->rate == CLOCK_33M)  in pci_enable()
265 		if (clk->rate == CLOCK_33M)  in pci_enable()
297 		if (clk->rates[i] == clk->rate) {  in clkout_enable()
298 			int shift = 14 - (2 * clk->module);  in clkout_enable()
299 			int enable = 7 - clk->module;  in clkout_enable()
309 	return -1;  in clkout_enable()
320 	clk->cl.dev_id = dev;  in clkdev_add_pmu()
321 	clk->cl.con_id = con;  in clkdev_add_pmu()
322 	clk->cl.clk = clk;  in clkdev_add_pmu()
323 	clk->enable = pmu_enable;  in clkdev_add_pmu()
324 	clk->disable = pmu_disable;  in clkdev_add_pmu()
325 	clk->module = module;  in clkdev_add_pmu()
326 	clk->bits = bits;  in clkdev_add_pmu()
334 	clkdev_add(&clk->cl);  in clkdev_add_pmu()
345 	clk->cl.dev_id = dev;  in clkdev_add_cgu()
346 	clk->cl.con_id = con;  in clkdev_add_cgu()
347 	clk->cl.clk = clk;  in clkdev_add_cgu()
348 	clk->enable = cgu_enable;  in clkdev_add_cgu()
349 	clk->disable = cgu_disable;  in clkdev_add_cgu()
350 	clk->bits = bits;  in clkdev_add_cgu()
351 	clkdev_add(&clk->cl);  in clkdev_add_cgu()
364 		clk->cl.dev_id = "17000000.pci";  in clkdev_add_pci()
365 		clk->cl.con_id = NULL;  in clkdev_add_pci()
366 		clk->cl.clk = clk;  in clkdev_add_pci()
367 		clk->rate = CLOCK_33M;  in clkdev_add_pci()
368 		clk->rates = valid_pci_rates;  in clkdev_add_pci()
369 		clk->enable = pci_enable;  in clkdev_add_pci()
370 		clk->disable = pmu_disable;  in clkdev_add_pci()
371 		clk->module = 0;  in clkdev_add_pci()
372 		clk->bits = PMU_PCI;  in clkdev_add_pci()
373 		clkdev_add(&clk->cl);  in clkdev_add_pci()
378 		clk_ext->cl.dev_id = "17000000.pci";  in clkdev_add_pci()
379 		clk_ext->cl.con_id = "external";  in clkdev_add_pci()
380 		clk_ext->cl.clk = clk_ext;  in clkdev_add_pci()
381 		clk_ext->enable = pci_ext_enable;  in clkdev_add_pci()
382 		clk_ext->disable = pci_ext_disable;  in clkdev_add_pci()
383 		clkdev_add(&clk_ext->cl);  in clkdev_add_pci()
387 /* xway socs can generate clocks on gpio pins */
413 		clk->cl.dev_id = "1f103000.cgu";  in clkdev_add_clkout()
414 		clk->cl.con_id = name;  in clkdev_add_clkout()
415 		clk->cl.clk = clk;  in clkdev_add_clkout()
416 		clk->rate = 0;  in clkdev_add_clkout()
417 		clk->rates = valid_clkout_rates[i];  in clkdev_add_clkout()
418 		clk->enable = clkout_enable;  in clkdev_add_clkout()
419 		clk->module = i;  in clkdev_add_clkout()
420 		clkdev_add(&clk->cl);  in clkdev_add_clkout()
429 			of_find_compatible_node(NULL, NULL, "lantiq,pmu-xway");  in ltq_soc_init()
431 			of_find_compatible_node(NULL, NULL, "lantiq,cgu-xway");  in ltq_soc_init()
433 			of_find_compatible_node(NULL, NULL, "lantiq,ebu-xway");  in ltq_soc_init()
467 	/* add our generic xway clocks */  in ltq_soc_init()
474 	clkdev_add_pmu("1e105300.ebu", NULL, 0, 0, PMU_EBU);  in ltq_soc_init()
493 		clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 2, PMU_ANALOG_USB0_P);  in ltq_soc_init()
494 		clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 2, PMU_ANALOG_USB1_P);  in ltq_soc_init()
515 		clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);  in ltq_soc_init()
549 		clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);  in ltq_soc_init()
551 		clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 0, PMU_USB1_P);  in ltq_soc_init()
573 		clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);  in ltq_soc_init()
575 		clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 0, PMU_USB1_P);  in ltq_soc_init()
586 		clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);  in ltq_soc_init()