Lines Matching +full:0 +full:xd4000000
185 i = 0; in show_stacktrace()
187 if (i && ((i % (64 / field)) == 0)) { in show_stacktrace()
201 pr_cont(" %0*lx", field, stackdata); in show_stacktrace()
215 regs.regs[31] = 0; in show_stack()
216 regs.cp0_epc = 0; in show_stack()
220 regs.regs[31] = 0; in show_stack()
275 for (i = 0; i < 32; ) { in __show_regs()
276 if ((i % 4) == 0) in __show_regs()
278 if (i == 0) in __show_regs()
279 pr_cont(" %0*lx", field, 0UL); in __show_regs()
283 pr_cont(" %0*lx", field, regs->regs[i]); in __show_regs()
286 if ((i % 4) == 0) in __show_regs()
291 printk("Acx : %0*lx\n", field, regs->acx); in __show_regs()
294 printk("Hi : %0*lx\n", field, regs->hi); in __show_regs()
295 printk("Lo : %0*lx\n", field, regs->lo); in __show_regs()
301 printk("epc : %0*lx %pS\n", field, regs->cp0_epc, in __show_regs()
303 printk("ra : %0*lx %pS\n", field, regs->regs[31], in __show_regs()
355 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); in __show_regs()
376 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", in show_registers()
384 printk("*HwTLS: %0*lx\n", field, tls); in show_registers()
401 if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr, in die()
403 sig = 0; in die()
484 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", in do_be()
487 if (notify_die(DIE_OOPS, "bus error", regs, 0, current->thread.trap_nr, in do_be()
502 #define OPCODE 0xfc000000
503 #define BASE 0x03e00000
504 #define RT 0x001f0000
505 #define OFFSET 0x0000ffff
506 #define LL 0xc0000000
507 #define SC 0xe0000000
508 #define SPEC0 0x00000000
509 #define SPEC3 0x7c000000
510 #define RD 0x0000f800
511 #define FUNC 0x0000003f
512 #define SYNC 0x0000000f
513 #define RDHWR 0x0000003b
516 #define MM_POOL32A_FUNC 0xfc00ffff
517 #define MM_RDHWR 0x00006b3c
518 #define MM_RS 0x001f0000
519 #define MM_RT 0x03e00000
556 ll_bit = 0; in simulate_ll()
564 return 0; in simulate_ll()
592 if (ll_bit == 0 || ll_task != current) { in simulate_sc()
593 regs->regs[reg] = 0; in simulate_sc()
595 return 0; in simulate_sc()
605 return 0; in simulate_sc()
619 1, regs, 0); in simulate_llsc()
624 1, regs, 0); in simulate_llsc()
640 1, regs, 0); in simulate_rdhwr()
644 return 0; in simulate_rdhwr()
648 return 0; in simulate_rdhwr()
651 return 0; in simulate_rdhwr()
661 return 0; in simulate_rdhwr()
664 return 0; in simulate_rdhwr()
677 return 0; in simulate_rdhwr_normal()
690 return 0; in simulate_rdhwr_mm()
701 1, regs, 0); in simulate_sync()
702 return 0; in simulate_sync()
714 #define LWC2 0xc8000000
716 #define CSR_OPCODE2 0x00000118
717 #define CSR_OPCODE2_MASK 0x000007ff
719 #define CSR_FUNC_CPUCFG 0x8
733 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0); in simulate_loongson3_cpucfg()
744 return 0; in simulate_loongson3_cpucfg()
795 case 0: in process_fpemu_return()
796 return 0; in process_fpemu_return()
868 return 0; in simulate_fp()
881 if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr, in do_fpe()
936 if (mt_fpemul_threshold > 0 && in mt_ase_fp_affinity()
1035 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; in do_bp()
1039 if (__get_inst16(&instr[0], (u16 *)epc, user)) in do_bp()
1044 bcode = (instr[0] >> 5) & 0x3f; in do_bp()
1045 } else if (mm_insn_16bit(instr[0])) { in do_bp()
1047 bcode = instr[0] & 0xf; in do_bp()
1052 opcode = (instr[0] << 16) | instr[1]; in do_bp()
1116 u32 opcode, tcode = 0; in do_tr()
1123 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; in do_tr()
1125 if (__get_inst16(&instr[0], (u16 *)(epc + 0), user) || in do_tr()
1128 opcode = (instr[0] << 16) | instr[1]; in do_tr()
1140 do_trap_or_bp(regs, tcode, 0, "Trap"); in do_tr()
1157 unsigned int opcode = 0; in do_ri()
1166 likely(get_user(opcode, epc) >= 0)) { in do_ri()
1167 unsigned long fcr31 = 0; in do_ri()
1171 case 0: in do_ri()
1187 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; in do_ri()
1189 if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr, in do_ri()
1195 if (unlikely(compute_return_epc(regs) < 0)) in do_ri()
1199 if (unlikely(get_user(opcode, epc) < 0)) in do_ri()
1202 if (!cpu_has_llsc && status < 0) in do_ri()
1205 if (status < 0) in do_ri()
1208 if (status < 0) in do_ri()
1211 if (status < 0) in do_ri()
1215 if (status < 0) in do_ri()
1219 unsigned short mmop[2] = { 0 }; in do_ri()
1221 if (unlikely(get_user(mmop[0], (u16 __user *)epc + 0) < 0)) in do_ri()
1223 if (unlikely(get_user(mmop[1], (u16 __user *)epc + 1) < 0)) in do_ri()
1225 opcode = mmop[0]; in do_ri()
1228 if (status < 0) in do_ri()
1232 if (status < 0) in do_ri()
1235 if (unlikely(status > 0)) { in do_ri()
1246 * No lock; only written during early bootup by CPU 0.
1342 err = own_fpu_inatomic(0); in enable_restore_fp_context()
1390 return 0; in enable_restore_fp_context()
1418 case 0: in do_cpu()
1422 opcode = 0; in do_cpu()
1425 if (unlikely(compute_return_epc(regs) < 0)) in do_cpu()
1429 if (unlikely(get_user(opcode, epc) < 0)) in do_cpu()
1432 if (!cpu_has_llsc && status < 0) in do_cpu()
1436 if (status < 0) in do_cpu()
1439 if (unlikely(status > 0)) { in do_cpu()
1471 err = enable_restore_fp_context(0); in do_cpu()
1476 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0, in do_cpu()
1512 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; in do_msa_fpe()
1513 if (notify_die(DIE_MSAFP, "MSA FP exception", regs, 0, in do_msa_fpe()
1619 case 0: in do_mt()
1665 (regs->cp0_cause & 0x7f) >> 2); in do_reserved()
1671 l1parity = 0; in nol1parity()
1678 l2parity = 0; in nol2parity()
1689 #define ERRCTL_PE 0x80000000 in parity_protection_init()
1690 #define ERRCTL_L2P 0x00800000 in parity_protection_init()
1721 l1parity = l2parity = 0; in parity_protection_init()
1814 write_c0_ecc(0x80000000); in parity_protection_init()
1818 (read_c0_ecc() & 0x80000000) ? "en" : "dis"); in parity_protection_init()
1839 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); in cache_parity_error()
1847 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) { in cache_parity_error()
1867 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); in cache_parity_error()
1871 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); in cache_parity_error()
1874 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); in cache_parity_error()
1887 (((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS) || in do_ftlb()
1888 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_LOONGSON))) { in do_ftlb()
1889 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n", in do_ftlb()
1891 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); in do_ftlb()
1895 if ((reg_val & 0xc0000000) == 0xc0000000) { in do_ftlb()
1918 case 0x08: in do_gsexc()
1953 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); in ejtag_exception_handler()
1954 if (debug & 0x80000000) { in ejtag_exception_handler()
1972 #if 0 in ejtag_exception_handler()
1974 write_c0_debug(debug | 0x100); in ejtag_exception_handler()
1980 * No lock; only written during early bootup by CPU 0.
1994 raw_notifier_call_chain(&nmi_chain, 0, regs); in nmi_exception_handler()
2026 if (!(handler & 0x1)) in set_except_vector()
2031 if (n == 0 && cpu_has_divec) { in set_except_vector()
2037 u32 *buf = (u32 *)(ebase + 0x200); in set_except_vector()
2039 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { in set_except_vector()
2047 local_flush_icache_range(ebase + 0x200, (unsigned long)buf); in set_except_vector()
2070 srs = 0; in set_vi_srs_handler()
2075 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); in set_vi_srs_handler()
2086 change_c0_srsmap(0xf << n*4, srs << n*4); in set_vi_srs_handler()
2089 if (srs == 0) { in set_vi_srs_handler()
2123 *h = (handler >> 16) & 0xffff; in set_vi_srs_handler()
2125 *h = (handler & 0xffff); in set_vi_srs_handler()
2140 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1); in set_vi_srs_handler()
2142 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2); in set_vi_srs_handler()
2144 h[0] = (insn >> 16) & 0xffff; in set_vi_srs_handler()
2145 h[1] = insn & 0xffff; in set_vi_srs_handler()
2146 h[2] = 0; in set_vi_srs_handler()
2147 h[3] = 0; in set_vi_srs_handler()
2157 return set_vi_srs_handler(n, addr, 0); in set_vi_handler()
2253 change_c0_intctl(0x3e0, VECTORSPACING); in configure_exception_vector()
2297 cpu_data[cpu].asid_cache = 0; in per_cpu_trap_init()
2364 vec_size = 0x400; in trap_init()
2367 vec_size = 0x200 + VECTORSPACING*64; in trap_init()
2373 panic("%s: Failed to allocate %lu bytes align=0x%x\n", in trap_init()
2387 if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000)) in trap_init()
2412 set_handler(0x180, &except_vec3_generic, 0x80); in trap_init()
2417 for (i = 0; i <= 31; i++) in trap_init()
2438 for (i = 0; i < nvec; i++) in trap_init()
2442 set_handler(0x200, &except_vec4, 0x8); in trap_init()
2522 set_handler(0x180, &except_vec3_r4000, 0x100); in trap_init()
2524 set_handler(0x180, &except_vec3_generic, 0x80); in trap_init()
2526 set_handler(0x080, &except_vec3_generic, 0x80); in trap_init()
2532 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */ in trap_init()