315 				    struct hw_perf_event *hwc)  in mipsxx_pmu_alloc_counter()  argument
325 		cntr_mask = (hwc->event_base >> 10) & 0xffff;  in mipsxx_pmu_alloc_counter()
327 		cntr_mask = (hwc->event_base >> 8) & 0xffff;  in mipsxx_pmu_alloc_counter()
410 				    struct hw_perf_event *hwc,  in mipspmu_event_set_period()  argument
413 	u64 left = local64_read(&hwc->period_left);  in mipspmu_event_set_period()
414 	u64 period = hwc->sample_period;  in mipspmu_event_set_period()
420 		local64_set(&hwc->period_left, left);  in mipspmu_event_set_period()
421 		hwc->last_period = period;  in mipspmu_event_set_period()
426 		local64_set(&hwc->period_left, left);  in mipspmu_event_set_period()
427 		hwc->last_period = period;  in mipspmu_event_set_period()
433 		local64_set(&hwc->period_left, left);  in mipspmu_event_set_period()
436 	local64_set(&hwc->prev_count, mipspmu.overflow - left);  in mipspmu_event_set_period()
440 				M_PERFCTL_EVENT(hwc->event_base & 0x3ff));  in mipspmu_event_set_period()
450 				 struct hw_perf_event *hwc,  in mipspmu_event_update()  argument
457 	prev_raw_count = local64_read(&hwc->prev_count);  in mipspmu_event_update()
460 	if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,  in mipspmu_event_update()
467 	local64_sub(delta, &hwc->period_left);  in mipspmu_event_update()
472 	struct hw_perf_event *hwc = &event->hw;  in mipspmu_start()  local
475 		WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));  in mipspmu_start()
477 	hwc->state = 0;  in mipspmu_start()
480 	mipspmu_event_set_period(event, hwc, hwc->idx);  in mipspmu_start()
483 	mipsxx_pmu_enable_event(hwc, hwc->idx);  in mipspmu_start()
488 	struct hw_perf_event *hwc = &event->hw;  in mipspmu_stop()  local
490 	if (!(hwc->state & PERF_HES_STOPPED)) {  in mipspmu_stop()
492 		mipsxx_pmu_disable_event(hwc->idx);  in mipspmu_stop()
494 		mipspmu_event_update(event, hwc, hwc->idx);  in mipspmu_stop()
495 		hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;  in mipspmu_stop()
502 	struct hw_perf_event *hwc = &event->hw;  in mipspmu_add()  local
509 	idx = mipsxx_pmu_alloc_counter(cpuc, hwc);  in mipspmu_add()
523 	hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;  in mipspmu_add()
538 	struct hw_perf_event *hwc = &event->hw;  in mipspmu_del()  local
539 	int idx = hwc->idx;  in mipspmu_del()
552 	struct hw_perf_event *hwc = &event->hw;  in mipspmu_read()  local
555 	if (hwc->idx < 0)  in mipspmu_read()
558 	mipspmu_event_update(event, hwc, hwc->idx);  in mipspmu_read()
787 	struct hw_perf_event *hwc = &event->hw;  in handle_associated_event()  local
789 	mipspmu_event_update(event, hwc, idx);  in handle_associated_event()
791 	if (!mipspmu_event_set_period(event, hwc, idx))  in handle_associated_event()
1474 	struct hw_perf_event *hwc = &event->hw;  in __hw_perf_event_init()  local
1504 	hwc->config_base = MIPS_PERFCTRL_IE;  in __hw_perf_event_init()
1506 	hwc->event_base = mipspmu_perf_event_encode(pev);  in __hw_perf_event_init()
1511 		hwc->config_base |= MIPS_PERFCTRL_U;  in __hw_perf_event_init()
1513 		hwc->config_base |= MIPS_PERFCTRL_K;  in __hw_perf_event_init()
1515 		hwc->config_base |= MIPS_PERFCTRL_EXL;  in __hw_perf_event_init()
1518 		hwc->config_base |= MIPS_PERFCTRL_S;  in __hw_perf_event_init()
1520 	hwc->config_base &= M_PERFCTL_CONFIG_MASK;  in __hw_perf_event_init()
1525 	hwc->idx = -1;  in __hw_perf_event_init()
1526 	hwc->config = 0;  in __hw_perf_event_init()
1528 	if (!hwc->sample_period) {  in __hw_perf_event_init()
1529 		hwc->sample_period  = mipspmu.max_period;  in __hw_perf_event_init()
1530 		hwc->last_period    = hwc->sample_period;  in __hw_perf_event_init()
1531 		local64_set(&hwc->period_left, hwc->sample_period);  in __hw_perf_event_init()