Lines Matching +full:0 +full:- +full:2
28 #include <asm/mips-r2-to-r6-emul.h>
59 int mipsr2_emulation = 0;
65 pr_info("MIPS R2-to-R6 Emulator Enabled!"); in mipsr2emu_enable()
72 * mipsr6_emul - Emulate some frequent R2/R5/R6 instructions in delay slot
83 regs->regs[MIPSInst_RT(ir)] = in mipsr6_emul()
84 (s32)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
86 return 0; in mipsr6_emul()
92 regs->regs[MIPSInst_RT(ir)] = in mipsr6_emul()
93 (s64)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
95 return 0; in mipsr6_emul()
101 return -SIGFPE; in mipsr6_emul()
106 regs->regs[MIPSInst_RD(ir)] = in mipsr6_emul()
107 regs->regs[MIPSInst_RS(ir)] | in mipsr6_emul()
108 regs->regs[MIPSInst_RT(ir)]; in mipsr6_emul()
109 return 0; in mipsr6_emul()
115 regs->regs[MIPSInst_RD(ir)] = in mipsr6_emul()
116 (s32)(((u32)regs->regs[MIPSInst_RT(ir)]) << in mipsr6_emul()
118 return 0; in mipsr6_emul()
124 regs->regs[MIPSInst_RD(ir)] = in mipsr6_emul()
125 (s32)(((u32)regs->regs[MIPSInst_RT(ir)]) >> in mipsr6_emul()
127 return 0; in mipsr6_emul()
133 regs->regs[MIPSInst_RD(ir)] = in mipsr6_emul()
134 (s32)((u32)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
135 (u32)regs->regs[MIPSInst_RT(ir)]); in mipsr6_emul()
136 return 0; in mipsr6_emul()
142 regs->regs[MIPSInst_RD(ir)] = in mipsr6_emul()
143 (s32)((u32)regs->regs[MIPSInst_RS(ir)] - in mipsr6_emul()
144 (u32)regs->regs[MIPSInst_RT(ir)]); in mipsr6_emul()
145 return 0; in mipsr6_emul()
151 regs->regs[MIPSInst_RD(ir)] = in mipsr6_emul()
152 (s64)(((u64)regs->regs[MIPSInst_RT(ir)]) << in mipsr6_emul()
154 return 0; in mipsr6_emul()
160 regs->regs[MIPSInst_RD(ir)] = in mipsr6_emul()
161 (s64)(((u64)regs->regs[MIPSInst_RT(ir)]) >> in mipsr6_emul()
163 return 0; in mipsr6_emul()
169 regs->regs[MIPSInst_RD(ir)] = in mipsr6_emul()
170 (u64)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
171 (u64)regs->regs[MIPSInst_RT(ir)]; in mipsr6_emul()
172 return 0; in mipsr6_emul()
178 regs->regs[MIPSInst_RD(ir)] = in mipsr6_emul()
179 (s64)((u64)regs->regs[MIPSInst_RS(ir)] - in mipsr6_emul()
180 (u64)regs->regs[MIPSInst_RT(ir)]); in mipsr6_emul()
181 return 0; in mipsr6_emul()
185 pr_debug("No fastpath BD emulation for instruction 0x%08x (op: %02x)\n", in mipsr6_emul()
193 * movf_func - Emulate a MOVF instruction
197 * Returns 0 since it always succeeds.
204 csr = current->thread.fpu.fcr31; in movf_func()
205 cond = fpucondbit[MIPSInst_RT(ir) >> 2]; in movf_func()
207 if (((csr & cond) == 0) && MIPSInst_RD(ir)) in movf_func()
208 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)]; in movf_func()
212 return 0; in movf_func()
216 * movt_func - Emulate a MOVT instruction
220 * Returns 0 since it always succeeds.
227 csr = current->thread.fpu.fcr31; in movt_func()
228 cond = fpucondbit[MIPSInst_RT(ir) >> 2]; in movt_func()
230 if (((csr & cond) != 0) && MIPSInst_RD(ir)) in movt_func()
231 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)]; in movt_func()
235 return 0; in movt_func()
239 * jr_func - Emulate a JR instruction.
245 * userland instruction or 0 on success.
257 nepc = regs->cp0_epc; in jr_func()
259 regs->cp0_epc -= 4; in jr_func()
260 epc = regs->cp0_epc; in jr_func()
263 if (err < 0) in jr_func()
268 cepc = regs->cp0_epc; in jr_func()
277 /* If nir == 0(NOP), then nothing else to do */ in jr_func()
280 * Negative err means FPU instruction in BD-slot, in jr_func()
281 * Zero err means 'BD-slot emulation done' in jr_func()
285 if (err > 0) { in jr_func()
286 regs->cp0_epc = nepc; in jr_func()
298 * movz_func - Emulate a MOVZ instruction
302 * Returns 0 since it always succeeds.
306 if (((regs->regs[MIPSInst_RT(ir)]) == 0) && MIPSInst_RD(ir)) in movz_func()
307 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)]; in movz_func()
310 return 0; in movz_func()
314 * movn_func - Emulate a MOVZ instruction
318 * Returns 0 since it always succeeds.
322 if (((regs->regs[MIPSInst_RT(ir)]) != 0) && MIPSInst_RD(ir)) in movn_func()
323 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)]; in movn_func()
326 return 0; in movn_func()
330 * mfhi_func - Emulate a MFHI instruction
334 * Returns 0 since it always succeeds.
339 regs->regs[MIPSInst_RD(ir)] = regs->hi; in mfhi_func()
343 return 0; in mfhi_func()
347 * mthi_func - Emulate a MTHI instruction
351 * Returns 0 since it always succeeds.
355 regs->hi = regs->regs[MIPSInst_RS(ir)]; in mthi_func()
359 return 0; in mthi_func()
363 * mflo_func - Emulate a MFLO instruction
367 * Returns 0 since it always succeeds.
372 regs->regs[MIPSInst_RD(ir)] = regs->lo; in mflo_func()
376 return 0; in mflo_func()
380 * mtlo_func - Emulate a MTLO instruction
384 * Returns 0 since it always succeeds.
388 regs->lo = regs->regs[MIPSInst_RS(ir)]; in mtlo_func()
392 return 0; in mtlo_func()
396 * mult_func - Emulate a MULT instruction
400 * Returns 0 since it always succeeds.
407 rt = regs->regs[MIPSInst_RT(ir)]; in mult_func()
408 rs = regs->regs[MIPSInst_RS(ir)]; in mult_func()
412 regs->lo = (s64)rs; in mult_func()
415 regs->hi = res; in mult_func()
419 return 0; in mult_func()
423 * multu_func - Emulate a MULTU instruction
427 * Returns 0 since it always succeeds.
434 rt = regs->regs[MIPSInst_RT(ir)]; in multu_func()
435 rs = regs->regs[MIPSInst_RS(ir)]; in multu_func()
438 regs->lo = (s64)(s32)rt; in multu_func()
439 regs->hi = (s64)(s32)(res >> 32); in multu_func()
443 return 0; in multu_func()
447 * div_func - Emulate a DIV instruction
451 * Returns 0 since it always succeeds.
457 rt = regs->regs[MIPSInst_RT(ir)]; in div_func()
458 rs = regs->regs[MIPSInst_RS(ir)]; in div_func()
460 regs->lo = (s64)(rs / rt); in div_func()
461 regs->hi = (s64)(rs % rt); in div_func()
465 return 0; in div_func()
469 * divu_func - Emulate a DIVU instruction
473 * Returns 0 since it always succeeds.
479 rt = regs->regs[MIPSInst_RT(ir)]; in divu_func()
480 rs = regs->regs[MIPSInst_RS(ir)]; in divu_func()
482 regs->lo = (s64)(rs / rt); in divu_func()
483 regs->hi = (s64)(rs % rt); in divu_func()
487 return 0; in divu_func()
491 * dmult_func - Emulate a DMULT instruction
495 * Returns 0 on success or SIGILL for 32-bit kernels.
505 rt = regs->regs[MIPSInst_RT(ir)]; in dmult_func()
506 rs = regs->regs[MIPSInst_RS(ir)]; in dmult_func()
509 regs->lo = res; in dmult_func()
511 "dmuh %0, %1, %2\t\n" in dmult_func()
515 regs->hi = res; in dmult_func()
519 return 0; in dmult_func()
523 * dmultu_func - Emulate a DMULTU instruction
527 * Returns 0 on success or SIGILL for 32-bit kernels.
537 rt = regs->regs[MIPSInst_RT(ir)]; in dmultu_func()
538 rs = regs->regs[MIPSInst_RS(ir)]; in dmultu_func()
541 regs->lo = res; in dmultu_func()
543 "dmuhu %0, %1, %2\t\n" in dmultu_func()
547 regs->hi = res; in dmultu_func()
551 return 0; in dmultu_func()
555 * ddiv_func - Emulate a DDIV instruction
559 * Returns 0 on success or SIGILL for 32-bit kernels.
568 rt = regs->regs[MIPSInst_RT(ir)]; in ddiv_func()
569 rs = regs->regs[MIPSInst_RS(ir)]; in ddiv_func()
571 regs->lo = rs / rt; in ddiv_func()
572 regs->hi = rs % rt; in ddiv_func()
576 return 0; in ddiv_func()
580 * ddivu_func - Emulate a DDIVU instruction
584 * Returns 0 on success or SIGILL for 32-bit kernels.
593 rt = regs->regs[MIPSInst_RT(ir)]; in ddivu_func()
594 rs = regs->regs[MIPSInst_RS(ir)]; in ddivu_func()
596 regs->lo = rs / rt; in ddivu_func()
597 regs->hi = rs % rt; in ddivu_func()
601 return 0; in ddivu_func()
606 { 0xfc1ff83f, 0x00000008, jr_func },
607 { 0xfc00ffff, 0x00000018, mult_func },
608 { 0xfc00ffff, 0x00000019, multu_func },
609 { 0xfc00ffff, 0x0000001c, dmult_func },
610 { 0xfc00ffff, 0x0000001d, dmultu_func },
611 { 0xffff07ff, 0x00000010, mfhi_func },
612 { 0xfc1fffff, 0x00000011, mthi_func },
613 { 0xffff07ff, 0x00000012, mflo_func },
614 { 0xfc1fffff, 0x00000013, mtlo_func },
615 { 0xfc0307ff, 0x00000001, movf_func },
616 { 0xfc0307ff, 0x00010001, movt_func },
617 { 0xfc0007ff, 0x0000000a, movz_func },
618 { 0xfc0007ff, 0x0000000b, movn_func },
619 { 0xfc00ffff, 0x0000001a, div_func },
620 { 0xfc00ffff, 0x0000001b, divu_func },
621 { 0xfc00ffff, 0x0000001e, ddiv_func },
622 { 0xfc00ffff, 0x0000001f, ddivu_func },
627 * madd_func - Emulate a MADD instruction
631 * Returns 0 since it always succeeds.
638 rt = regs->regs[MIPSInst_RT(ir)]; in madd_func()
639 rs = regs->regs[MIPSInst_RS(ir)]; in madd_func()
641 rt = regs->hi; in madd_func()
642 rs = regs->lo; in madd_func()
646 regs->lo = (s64)rt; in madd_func()
648 regs->hi = (s64)rs; in madd_func()
652 return 0; in madd_func()
656 * maddu_func - Emulate a MADDU instruction
660 * Returns 0 since it always succeeds.
667 rt = regs->regs[MIPSInst_RT(ir)]; in maddu_func()
668 rs = regs->regs[MIPSInst_RS(ir)]; in maddu_func()
670 rt = regs->hi; in maddu_func()
671 rs = regs->lo; in maddu_func()
675 regs->lo = (s64)(s32)rt; in maddu_func()
677 regs->hi = (s64)(s32)rs; in maddu_func()
681 return 0; in maddu_func()
685 * msub_func - Emulate a MSUB instruction
689 * Returns 0 since it always succeeds.
696 rt = regs->regs[MIPSInst_RT(ir)]; in msub_func()
697 rs = regs->regs[MIPSInst_RS(ir)]; in msub_func()
699 rt = regs->hi; in msub_func()
700 rs = regs->lo; in msub_func()
701 res = ((((s64)rt) << 32) | (u32)rs) - res; in msub_func()
704 regs->lo = (s64)rt; in msub_func()
706 regs->hi = (s64)rs; in msub_func()
710 return 0; in msub_func()
714 * msubu_func - Emulate a MSUBU instruction
718 * Returns 0 since it always succeeds.
725 rt = regs->regs[MIPSInst_RT(ir)]; in msubu_func()
726 rs = regs->regs[MIPSInst_RS(ir)]; in msubu_func()
728 rt = regs->hi; in msubu_func()
729 rs = regs->lo; in msubu_func()
730 res = ((((s64)rt) << 32) | (u32)rs) - res; in msubu_func()
733 regs->lo = (s64)(s32)rt; in msubu_func()
735 regs->hi = (s64)(s32)rs; in msubu_func()
739 return 0; in msubu_func()
743 * mul_func - Emulate a MUL instruction
747 * Returns 0 since it always succeeds.
755 return 0; in mul_func()
756 rt = regs->regs[MIPSInst_RT(ir)]; in mul_func()
757 rs = regs->regs[MIPSInst_RS(ir)]; in mul_func()
761 regs->regs[MIPSInst_RD(ir)] = (s64)rs; in mul_func()
765 return 0; in mul_func()
769 * clz_func - Emulate a CLZ instruction
773 * Returns 0 since it always succeeds.
781 return 0; in clz_func()
783 rs = regs->regs[MIPSInst_RS(ir)]; in clz_func()
784 __asm__ __volatile__("clz %0, %1" : "=r"(res) : "r"(rs)); in clz_func()
785 regs->regs[MIPSInst_RD(ir)] = res; in clz_func()
789 return 0; in clz_func()
793 * clo_func - Emulate a CLO instruction
797 * Returns 0 since it always succeeds.
806 return 0; in clo_func()
808 rs = regs->regs[MIPSInst_RS(ir)]; in clo_func()
809 __asm__ __volatile__("clo %0, %1" : "=r"(res) : "r"(rs)); in clo_func()
810 regs->regs[MIPSInst_RD(ir)] = res; in clo_func()
814 return 0; in clo_func()
818 * dclz_func - Emulate a DCLZ instruction
822 * Returns 0 since it always succeeds.
833 return 0; in dclz_func()
835 rs = regs->regs[MIPSInst_RS(ir)]; in dclz_func()
836 __asm__ __volatile__("dclz %0, %1" : "=r"(res) : "r"(rs)); in dclz_func()
837 regs->regs[MIPSInst_RD(ir)] = res; in dclz_func()
841 return 0; in dclz_func()
845 * dclo_func - Emulate a DCLO instruction
849 * Returns 0 since it always succeeds.
860 return 0; in dclo_func()
862 rs = regs->regs[MIPSInst_RS(ir)]; in dclo_func()
863 __asm__ __volatile__("dclo %0, %1" : "=r"(res) : "r"(rs)); in dclo_func()
864 regs->regs[MIPSInst_RD(ir)] = res; in dclo_func()
868 return 0; in dclo_func()
873 { 0xfc00ffff, 0x70000000, madd_func },
874 { 0xfc00ffff, 0x70000001, maddu_func },
875 { 0xfc0007ff, 0x70000002, mul_func },
876 { 0xfc00ffff, 0x70000004, msub_func },
877 { 0xfc00ffff, 0x70000005, msubu_func },
878 { 0xfc0007ff, 0x70000020, clz_func },
879 { 0xfc0007ff, 0x70000021, clo_func },
880 { 0xfc0007ff, 0x70000024, dclz_func },
881 { 0xfc0007ff, 0x70000025, dclo_func },
891 for (p = table; p->func; p++) { in mipsr2_find_op_func()
892 if ((inst & p->mask) == p->code) { in mipsr2_find_op_func()
893 err = (p->func)(regs, inst); in mipsr2_find_op_func()
908 int err = 0; in mipsr2_decoder()
914 int pass = 0; in mipsr2_decoder()
917 r31 = regs->regs[31]; in mipsr2_decoder()
918 epc = regs->cp0_epc; in mipsr2_decoder()
920 if (err < 0) { in mipsr2_decoder()
924 pr_debug("Emulating the 0x%08x R2 instruction @ 0x%08lx (pass=%d))\n", in mipsr2_decoder()
930 if (err < 0) { in mipsr2_decoder()
932 regs->cp0_cause |= CAUSEF_BD; in mipsr2_decoder()
944 if ((long)regs->regs[rs] >= MIPSInst_SIMM(inst)) in mipsr2_decoder()
945 do_trap_or_bp(regs, 0, 0, "TGEI"); in mipsr2_decoder()
951 if (regs->regs[rs] >= MIPSInst_UIMM(inst)) in mipsr2_decoder()
952 do_trap_or_bp(regs, 0, 0, "TGEIU"); in mipsr2_decoder()
958 if ((long)regs->regs[rs] < MIPSInst_SIMM(inst)) in mipsr2_decoder()
959 do_trap_or_bp(regs, 0, 0, "TLTI"); in mipsr2_decoder()
965 if (regs->regs[rs] < MIPSInst_UIMM(inst)) in mipsr2_decoder()
966 do_trap_or_bp(regs, 0, 0, "TLTIU"); in mipsr2_decoder()
972 if (regs->regs[rs] == MIPSInst_SIMM(inst)) in mipsr2_decoder()
973 do_trap_or_bp(regs, 0, 0, "TEQI"); in mipsr2_decoder()
979 if (regs->regs[rs] != MIPSInst_SIMM(inst)) in mipsr2_decoder()
980 do_trap_or_bp(regs, 0, 0, "TNEI"); in mipsr2_decoder()
993 regs->regs[31] = r31; in mipsr2_decoder()
994 regs->cp0_epc = epc; in mipsr2_decoder()
996 if (err < 0) in mipsr2_decoder()
1000 cpc = regs->cp0_epc; in mipsr2_decoder()
1031 regs->cp0_cause |= CAUSEF_BD; in mipsr2_decoder()
1036 if (err > 0) { in mipsr2_decoder()
1050 regs->regs[31] = r31; in mipsr2_decoder()
1051 regs->cp0_epc = epc; in mipsr2_decoder()
1053 if (err < 0) in mipsr2_decoder()
1055 cpc = regs->cp0_epc; in mipsr2_decoder()
1080 regs->cp0_cause |= CAUSEF_BD; in mipsr2_decoder()
1085 if (err > 0) { in mipsr2_decoder()
1094 regs->regs[31] = r31; in mipsr2_decoder()
1095 regs->cp0_epc = epc; in mipsr2_decoder()
1104 * For BLEZL and BGTZL, rt field must be set to 0. If this in mipsr2_decoder()
1119 regs->regs[31] = r31; in mipsr2_decoder()
1120 regs->cp0_epc = epc; in mipsr2_decoder()
1122 if (err < 0) in mipsr2_decoder()
1126 cpc = regs->cp0_epc; in mipsr2_decoder()
1157 regs->cp0_cause |= CAUSEF_BD; in mipsr2_decoder()
1162 if (err > 0) { in mipsr2_decoder()
1175 regs->regs[31] = r31; in mipsr2_decoder()
1176 regs->cp0_epc = epc; in mipsr2_decoder()
1178 err = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0, in mipsr2_decoder()
1185 *fcr31 = res = mask_fcr31_x(current->thread.fpu.fcr31); in mipsr2_decoder()
1186 current->thread.fpu.fcr31 &= ~res; in mipsr2_decoder()
1189 * this is a tricky issue - lose_fpu() uses LL/SC atomics in mipsr2_decoder()
1193 * more often than LL-FPU-SC and I prefer loop here until in mipsr2_decoder()
1199 current->thread.cp0_baduaddr = (unsigned long)fault_addr; in mipsr2_decoder()
1206 rt = regs->regs[MIPSInst_RT(inst)]; in mipsr2_decoder()
1207 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
1209 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
1217 "1:" LB "%1, 0(%2)\n" in mipsr2_decoder()
1218 INS "%0, %1, 24, 8\n" in mipsr2_decoder()
1219 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1220 " beq $0, %1, 9f\n" in mipsr2_decoder()
1221 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1222 "2:" LB "%1, 0(%2)\n" in mipsr2_decoder()
1223 INS "%0, %1, 16, 8\n" in mipsr2_decoder()
1224 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1225 " beq $0, %1, 9f\n" in mipsr2_decoder()
1226 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1227 "3:" LB "%1, 0(%2)\n" in mipsr2_decoder()
1228 INS "%0, %1, 8, 8\n" in mipsr2_decoder()
1229 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1230 " beq $0, %1, 9f\n" in mipsr2_decoder()
1231 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1232 "4:" LB "%1, 0(%2)\n" in mipsr2_decoder()
1233 INS "%0, %1, 0, 8\n" in mipsr2_decoder()
1235 "1:" LB "%1, 0(%2)\n" in mipsr2_decoder()
1236 INS "%0, %1, 24, 8\n" in mipsr2_decoder()
1237 ADDIU "%2, %2, 1\n" in mipsr2_decoder()
1238 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1239 " beq $0, %1, 9f\n" in mipsr2_decoder()
1240 "2:" LB "%1, 0(%2)\n" in mipsr2_decoder()
1241 INS "%0, %1, 16, 8\n" in mipsr2_decoder()
1242 ADDIU "%2, %2, 1\n" in mipsr2_decoder()
1243 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1244 " beq $0, %1, 9f\n" in mipsr2_decoder()
1245 "3:" LB "%1, 0(%2)\n" in mipsr2_decoder()
1246 INS "%0, %1, 8, 8\n" in mipsr2_decoder()
1247 ADDIU "%2, %2, 1\n" in mipsr2_decoder()
1248 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1249 " beq $0, %1, 9f\n" in mipsr2_decoder()
1250 "4:" LB "%1, 0(%2)\n" in mipsr2_decoder()
1251 INS "%0, %1, 0, 8\n" in mipsr2_decoder()
1253 "9: sll %0, %0, 0\n" in mipsr2_decoder()
1262 STR(PTR_WD) " 2b,8b\n" in mipsr2_decoder()
1272 regs->regs[MIPSInst_RT(inst)] = rt; in mipsr2_decoder()
1279 rt = regs->regs[MIPSInst_RT(inst)]; in mipsr2_decoder()
1280 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
1282 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
1290 "1:" LB "%1, 0(%2)\n" in mipsr2_decoder()
1291 INS "%0, %1, 0, 8\n" in mipsr2_decoder()
1292 ADDIU "%2, %2, 1\n" in mipsr2_decoder()
1293 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1294 " beq $0, %1, 9f\n" in mipsr2_decoder()
1295 "2:" LB "%1, 0(%2)\n" in mipsr2_decoder()
1296 INS "%0, %1, 8, 8\n" in mipsr2_decoder()
1297 ADDIU "%2, %2, 1\n" in mipsr2_decoder()
1298 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1299 " beq $0, %1, 9f\n" in mipsr2_decoder()
1300 "3:" LB "%1, 0(%2)\n" in mipsr2_decoder()
1301 INS "%0, %1, 16, 8\n" in mipsr2_decoder()
1302 ADDIU "%2, %2, 1\n" in mipsr2_decoder()
1303 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1304 " beq $0, %1, 9f\n" in mipsr2_decoder()
1305 "4:" LB "%1, 0(%2)\n" in mipsr2_decoder()
1306 INS "%0, %1, 24, 8\n" in mipsr2_decoder()
1307 " sll %0, %0, 0\n" in mipsr2_decoder()
1309 "1:" LB "%1, 0(%2)\n" in mipsr2_decoder()
1310 INS "%0, %1, 0, 8\n" in mipsr2_decoder()
1311 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1312 " beq $0, %1, 9f\n" in mipsr2_decoder()
1313 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1314 "2:" LB "%1, 0(%2)\n" in mipsr2_decoder()
1315 INS "%0, %1, 8, 8\n" in mipsr2_decoder()
1316 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1317 " beq $0, %1, 9f\n" in mipsr2_decoder()
1318 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1319 "3:" LB "%1, 0(%2)\n" in mipsr2_decoder()
1320 INS "%0, %1, 16, 8\n" in mipsr2_decoder()
1321 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1322 " beq $0, %1, 9f\n" in mipsr2_decoder()
1323 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1324 "4:" LB "%1, 0(%2)\n" in mipsr2_decoder()
1325 INS "%0, %1, 24, 8\n" in mipsr2_decoder()
1326 " sll %0, %0, 0\n" in mipsr2_decoder()
1337 STR(PTR_WD) " 2b,8b\n" in mipsr2_decoder()
1346 regs->regs[MIPSInst_RT(inst)] = rt; in mipsr2_decoder()
1353 rt = regs->regs[MIPSInst_RT(inst)]; in mipsr2_decoder()
1354 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
1356 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
1364 EXT "%1, %0, 24, 8\n" in mipsr2_decoder()
1365 "1:" SB "%1, 0(%2)\n" in mipsr2_decoder()
1366 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1367 " beq $0, %1, 9f\n" in mipsr2_decoder()
1368 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1369 EXT "%1, %0, 16, 8\n" in mipsr2_decoder()
1370 "2:" SB "%1, 0(%2)\n" in mipsr2_decoder()
1371 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1372 " beq $0, %1, 9f\n" in mipsr2_decoder()
1373 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1374 EXT "%1, %0, 8, 8\n" in mipsr2_decoder()
1375 "3:" SB "%1, 0(%2)\n" in mipsr2_decoder()
1376 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1377 " beq $0, %1, 9f\n" in mipsr2_decoder()
1378 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1379 EXT "%1, %0, 0, 8\n" in mipsr2_decoder()
1380 "4:" SB "%1, 0(%2)\n" in mipsr2_decoder()
1382 EXT "%1, %0, 24, 8\n" in mipsr2_decoder()
1383 "1:" SB "%1, 0(%2)\n" in mipsr2_decoder()
1384 ADDIU "%2, %2, 1\n" in mipsr2_decoder()
1385 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1386 " beq $0, %1, 9f\n" in mipsr2_decoder()
1387 EXT "%1, %0, 16, 8\n" in mipsr2_decoder()
1388 "2:" SB "%1, 0(%2)\n" in mipsr2_decoder()
1389 ADDIU "%2, %2, 1\n" in mipsr2_decoder()
1390 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1391 " beq $0, %1, 9f\n" in mipsr2_decoder()
1392 EXT "%1, %0, 8, 8\n" in mipsr2_decoder()
1393 "3:" SB "%1, 0(%2)\n" in mipsr2_decoder()
1394 ADDIU "%2, %2, 1\n" in mipsr2_decoder()
1395 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1396 " beq $0, %1, 9f\n" in mipsr2_decoder()
1397 EXT "%1, %0, 0, 8\n" in mipsr2_decoder()
1398 "4:" SB "%1, 0(%2)\n" in mipsr2_decoder()
1408 STR(PTR_WD) " 2b,8b\n" in mipsr2_decoder()
1423 rt = regs->regs[MIPSInst_RT(inst)]; in mipsr2_decoder()
1424 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
1426 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
1434 EXT "%1, %0, 0, 8\n" in mipsr2_decoder()
1435 "1:" SB "%1, 0(%2)\n" in mipsr2_decoder()
1436 ADDIU "%2, %2, 1\n" in mipsr2_decoder()
1437 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1438 " beq $0, %1, 9f\n" in mipsr2_decoder()
1439 EXT "%1, %0, 8, 8\n" in mipsr2_decoder()
1440 "2:" SB "%1, 0(%2)\n" in mipsr2_decoder()
1441 ADDIU "%2, %2, 1\n" in mipsr2_decoder()
1442 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1443 " beq $0, %1, 9f\n" in mipsr2_decoder()
1444 EXT "%1, %0, 16, 8\n" in mipsr2_decoder()
1445 "3:" SB "%1, 0(%2)\n" in mipsr2_decoder()
1446 ADDIU "%2, %2, 1\n" in mipsr2_decoder()
1447 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1448 " beq $0, %1, 9f\n" in mipsr2_decoder()
1449 EXT "%1, %0, 24, 8\n" in mipsr2_decoder()
1450 "4:" SB "%1, 0(%2)\n" in mipsr2_decoder()
1452 EXT "%1, %0, 0, 8\n" in mipsr2_decoder()
1453 "1:" SB "%1, 0(%2)\n" in mipsr2_decoder()
1454 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1455 " beq $0, %1, 9f\n" in mipsr2_decoder()
1456 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1457 EXT "%1, %0, 8, 8\n" in mipsr2_decoder()
1458 "2:" SB "%1, 0(%2)\n" in mipsr2_decoder()
1459 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1460 " beq $0, %1, 9f\n" in mipsr2_decoder()
1461 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1462 EXT "%1, %0, 16, 8\n" in mipsr2_decoder()
1463 "3:" SB "%1, 0(%2)\n" in mipsr2_decoder()
1464 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1465 " beq $0, %1, 9f\n" in mipsr2_decoder()
1466 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1467 EXT "%1, %0, 24, 8\n" in mipsr2_decoder()
1468 "4:" SB "%1, 0(%2)\n" in mipsr2_decoder()
1478 STR(PTR_WD) " 2b,8b\n" in mipsr2_decoder()
1498 rt = regs->regs[MIPSInst_RT(inst)]; in mipsr2_decoder()
1499 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
1501 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
1509 "1: lb %1, 0(%2)\n" in mipsr2_decoder()
1510 " dinsu %0, %1, 56, 8\n" in mipsr2_decoder()
1511 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1512 " beq $0, %1, 9f\n" in mipsr2_decoder()
1513 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1514 "2: lb %1, 0(%2)\n" in mipsr2_decoder()
1515 " dinsu %0, %1, 48, 8\n" in mipsr2_decoder()
1516 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1517 " beq $0, %1, 9f\n" in mipsr2_decoder()
1518 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1519 "3: lb %1, 0(%2)\n" in mipsr2_decoder()
1520 " dinsu %0, %1, 40, 8\n" in mipsr2_decoder()
1521 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1522 " beq $0, %1, 9f\n" in mipsr2_decoder()
1523 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1524 "4: lb %1, 0(%2)\n" in mipsr2_decoder()
1525 " dinsu %0, %1, 32, 8\n" in mipsr2_decoder()
1526 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1527 " beq $0, %1, 9f\n" in mipsr2_decoder()
1528 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1529 "5: lb %1, 0(%2)\n" in mipsr2_decoder()
1530 " dins %0, %1, 24, 8\n" in mipsr2_decoder()
1531 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1532 " beq $0, %1, 9f\n" in mipsr2_decoder()
1533 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1534 "6: lb %1, 0(%2)\n" in mipsr2_decoder()
1535 " dins %0, %1, 16, 8\n" in mipsr2_decoder()
1536 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1537 " beq $0, %1, 9f\n" in mipsr2_decoder()
1538 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1539 "7: lb %1, 0(%2)\n" in mipsr2_decoder()
1540 " dins %0, %1, 8, 8\n" in mipsr2_decoder()
1541 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1542 " beq $0, %1, 9f\n" in mipsr2_decoder()
1543 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1544 "0: lb %1, 0(%2)\n" in mipsr2_decoder()
1545 " dins %0, %1, 0, 8\n" in mipsr2_decoder()
1547 "1: lb %1, 0(%2)\n" in mipsr2_decoder()
1548 " dinsu %0, %1, 56, 8\n" in mipsr2_decoder()
1549 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1550 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1551 " beq $0, %1, 9f\n" in mipsr2_decoder()
1552 "2: lb %1, 0(%2)\n" in mipsr2_decoder()
1553 " dinsu %0, %1, 48, 8\n" in mipsr2_decoder()
1554 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1555 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1556 " beq $0, %1, 9f\n" in mipsr2_decoder()
1557 "3: lb %1, 0(%2)\n" in mipsr2_decoder()
1558 " dinsu %0, %1, 40, 8\n" in mipsr2_decoder()
1559 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1560 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1561 " beq $0, %1, 9f\n" in mipsr2_decoder()
1562 "4: lb %1, 0(%2)\n" in mipsr2_decoder()
1563 " dinsu %0, %1, 32, 8\n" in mipsr2_decoder()
1564 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1565 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1566 " beq $0, %1, 9f\n" in mipsr2_decoder()
1567 "5: lb %1, 0(%2)\n" in mipsr2_decoder()
1568 " dins %0, %1, 24, 8\n" in mipsr2_decoder()
1569 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1570 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1571 " beq $0, %1, 9f\n" in mipsr2_decoder()
1572 "6: lb %1, 0(%2)\n" in mipsr2_decoder()
1573 " dins %0, %1, 16, 8\n" in mipsr2_decoder()
1574 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1575 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1576 " beq $0, %1, 9f\n" in mipsr2_decoder()
1577 "7: lb %1, 0(%2)\n" in mipsr2_decoder()
1578 " dins %0, %1, 8, 8\n" in mipsr2_decoder()
1579 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1580 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1581 " beq $0, %1, 9f\n" in mipsr2_decoder()
1582 "0: lb %1, 0(%2)\n" in mipsr2_decoder()
1583 " dins %0, %1, 0, 8\n" in mipsr2_decoder()
1593 STR(PTR_WD) " 2b,8b\n" in mipsr2_decoder()
1599 STR(PTR_WD) " 0b,8b\n" in mipsr2_decoder()
1606 regs->regs[MIPSInst_RT(inst)] = rt; in mipsr2_decoder()
1617 rt = regs->regs[MIPSInst_RT(inst)]; in mipsr2_decoder()
1618 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
1620 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
1628 "1: lb %1, 0(%2)\n" in mipsr2_decoder()
1629 " dins %0, %1, 0, 8\n" in mipsr2_decoder()
1630 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1631 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1632 " beq $0, %1, 9f\n" in mipsr2_decoder()
1633 "2: lb %1, 0(%2)\n" in mipsr2_decoder()
1634 " dins %0, %1, 8, 8\n" in mipsr2_decoder()
1635 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1636 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1637 " beq $0, %1, 9f\n" in mipsr2_decoder()
1638 "3: lb %1, 0(%2)\n" in mipsr2_decoder()
1639 " dins %0, %1, 16, 8\n" in mipsr2_decoder()
1640 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1641 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1642 " beq $0, %1, 9f\n" in mipsr2_decoder()
1643 "4: lb %1, 0(%2)\n" in mipsr2_decoder()
1644 " dins %0, %1, 24, 8\n" in mipsr2_decoder()
1645 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1646 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1647 " beq $0, %1, 9f\n" in mipsr2_decoder()
1648 "5: lb %1, 0(%2)\n" in mipsr2_decoder()
1649 " dinsu %0, %1, 32, 8\n" in mipsr2_decoder()
1650 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1651 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1652 " beq $0, %1, 9f\n" in mipsr2_decoder()
1653 "6: lb %1, 0(%2)\n" in mipsr2_decoder()
1654 " dinsu %0, %1, 40, 8\n" in mipsr2_decoder()
1655 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1656 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1657 " beq $0, %1, 9f\n" in mipsr2_decoder()
1658 "7: lb %1, 0(%2)\n" in mipsr2_decoder()
1659 " dinsu %0, %1, 48, 8\n" in mipsr2_decoder()
1660 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1661 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1662 " beq $0, %1, 9f\n" in mipsr2_decoder()
1663 "0: lb %1, 0(%2)\n" in mipsr2_decoder()
1664 " dinsu %0, %1, 56, 8\n" in mipsr2_decoder()
1666 "1: lb %1, 0(%2)\n" in mipsr2_decoder()
1667 " dins %0, %1, 0, 8\n" in mipsr2_decoder()
1668 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1669 " beq $0, %1, 9f\n" in mipsr2_decoder()
1670 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1671 "2: lb %1, 0(%2)\n" in mipsr2_decoder()
1672 " dins %0, %1, 8, 8\n" in mipsr2_decoder()
1673 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1674 " beq $0, %1, 9f\n" in mipsr2_decoder()
1675 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1676 "3: lb %1, 0(%2)\n" in mipsr2_decoder()
1677 " dins %0, %1, 16, 8\n" in mipsr2_decoder()
1678 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1679 " beq $0, %1, 9f\n" in mipsr2_decoder()
1680 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1681 "4: lb %1, 0(%2)\n" in mipsr2_decoder()
1682 " dins %0, %1, 24, 8\n" in mipsr2_decoder()
1683 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1684 " beq $0, %1, 9f\n" in mipsr2_decoder()
1685 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1686 "5: lb %1, 0(%2)\n" in mipsr2_decoder()
1687 " dinsu %0, %1, 32, 8\n" in mipsr2_decoder()
1688 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1689 " beq $0, %1, 9f\n" in mipsr2_decoder()
1690 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1691 "6: lb %1, 0(%2)\n" in mipsr2_decoder()
1692 " dinsu %0, %1, 40, 8\n" in mipsr2_decoder()
1693 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1694 " beq $0, %1, 9f\n" in mipsr2_decoder()
1695 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1696 "7: lb %1, 0(%2)\n" in mipsr2_decoder()
1697 " dinsu %0, %1, 48, 8\n" in mipsr2_decoder()
1698 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1699 " beq $0, %1, 9f\n" in mipsr2_decoder()
1700 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1701 "0: lb %1, 0(%2)\n" in mipsr2_decoder()
1702 " dinsu %0, %1, 56, 8\n" in mipsr2_decoder()
1712 STR(PTR_WD) " 2b,8b\n" in mipsr2_decoder()
1718 STR(PTR_WD) " 0b,8b\n" in mipsr2_decoder()
1725 regs->regs[MIPSInst_RT(inst)] = rt; in mipsr2_decoder()
1736 rt = regs->regs[MIPSInst_RT(inst)]; in mipsr2_decoder()
1737 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
1739 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
1747 " dextu %1, %0, 56, 8\n" in mipsr2_decoder()
1748 "1: sb %1, 0(%2)\n" in mipsr2_decoder()
1749 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1750 " beq $0, %1, 9f\n" in mipsr2_decoder()
1751 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1752 " dextu %1, %0, 48, 8\n" in mipsr2_decoder()
1753 "2: sb %1, 0(%2)\n" in mipsr2_decoder()
1754 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1755 " beq $0, %1, 9f\n" in mipsr2_decoder()
1756 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1757 " dextu %1, %0, 40, 8\n" in mipsr2_decoder()
1758 "3: sb %1, 0(%2)\n" in mipsr2_decoder()
1759 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1760 " beq $0, %1, 9f\n" in mipsr2_decoder()
1761 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1762 " dextu %1, %0, 32, 8\n" in mipsr2_decoder()
1763 "4: sb %1, 0(%2)\n" in mipsr2_decoder()
1764 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1765 " beq $0, %1, 9f\n" in mipsr2_decoder()
1766 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1767 " dext %1, %0, 24, 8\n" in mipsr2_decoder()
1768 "5: sb %1, 0(%2)\n" in mipsr2_decoder()
1769 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1770 " beq $0, %1, 9f\n" in mipsr2_decoder()
1771 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1772 " dext %1, %0, 16, 8\n" in mipsr2_decoder()
1773 "6: sb %1, 0(%2)\n" in mipsr2_decoder()
1774 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1775 " beq $0, %1, 9f\n" in mipsr2_decoder()
1776 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1777 " dext %1, %0, 8, 8\n" in mipsr2_decoder()
1778 "7: sb %1, 0(%2)\n" in mipsr2_decoder()
1779 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1780 " beq $0, %1, 9f\n" in mipsr2_decoder()
1781 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1782 " dext %1, %0, 0, 8\n" in mipsr2_decoder()
1783 "0: sb %1, 0(%2)\n" in mipsr2_decoder()
1785 " dextu %1, %0, 56, 8\n" in mipsr2_decoder()
1786 "1: sb %1, 0(%2)\n" in mipsr2_decoder()
1787 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1788 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1789 " beq $0, %1, 9f\n" in mipsr2_decoder()
1790 " dextu %1, %0, 48, 8\n" in mipsr2_decoder()
1791 "2: sb %1, 0(%2)\n" in mipsr2_decoder()
1792 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1793 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1794 " beq $0, %1, 9f\n" in mipsr2_decoder()
1795 " dextu %1, %0, 40, 8\n" in mipsr2_decoder()
1796 "3: sb %1, 0(%2)\n" in mipsr2_decoder()
1797 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1798 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1799 " beq $0, %1, 9f\n" in mipsr2_decoder()
1800 " dextu %1, %0, 32, 8\n" in mipsr2_decoder()
1801 "4: sb %1, 0(%2)\n" in mipsr2_decoder()
1802 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1803 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1804 " beq $0, %1, 9f\n" in mipsr2_decoder()
1805 " dext %1, %0, 24, 8\n" in mipsr2_decoder()
1806 "5: sb %1, 0(%2)\n" in mipsr2_decoder()
1807 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1808 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1809 " beq $0, %1, 9f\n" in mipsr2_decoder()
1810 " dext %1, %0, 16, 8\n" in mipsr2_decoder()
1811 "6: sb %1, 0(%2)\n" in mipsr2_decoder()
1812 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1813 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1814 " beq $0, %1, 9f\n" in mipsr2_decoder()
1815 " dext %1, %0, 8, 8\n" in mipsr2_decoder()
1816 "7: sb %1, 0(%2)\n" in mipsr2_decoder()
1817 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1818 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1819 " beq $0, %1, 9f\n" in mipsr2_decoder()
1820 " dext %1, %0, 0, 8\n" in mipsr2_decoder()
1821 "0: sb %1, 0(%2)\n" in mipsr2_decoder()
1831 STR(PTR_WD) " 2b,8b\n" in mipsr2_decoder()
1837 STR(PTR_WD) " 0b,8b\n" in mipsr2_decoder()
1854 rt = regs->regs[MIPSInst_RT(inst)]; in mipsr2_decoder()
1855 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
1857 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
1865 " dext %1, %0, 0, 8\n" in mipsr2_decoder()
1866 "1: sb %1, 0(%2)\n" in mipsr2_decoder()
1867 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1868 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1869 " beq $0, %1, 9f\n" in mipsr2_decoder()
1870 " dext %1, %0, 8, 8\n" in mipsr2_decoder()
1871 "2: sb %1, 0(%2)\n" in mipsr2_decoder()
1872 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1873 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1874 " beq $0, %1, 9f\n" in mipsr2_decoder()
1875 " dext %1, %0, 16, 8\n" in mipsr2_decoder()
1876 "3: sb %1, 0(%2)\n" in mipsr2_decoder()
1877 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1878 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1879 " beq $0, %1, 9f\n" in mipsr2_decoder()
1880 " dext %1, %0, 24, 8\n" in mipsr2_decoder()
1881 "4: sb %1, 0(%2)\n" in mipsr2_decoder()
1882 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1883 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1884 " beq $0, %1, 9f\n" in mipsr2_decoder()
1885 " dextu %1, %0, 32, 8\n" in mipsr2_decoder()
1886 "5: sb %1, 0(%2)\n" in mipsr2_decoder()
1887 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1888 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1889 " beq $0, %1, 9f\n" in mipsr2_decoder()
1890 " dextu %1, %0, 40, 8\n" in mipsr2_decoder()
1891 "6: sb %1, 0(%2)\n" in mipsr2_decoder()
1892 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1893 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1894 " beq $0, %1, 9f\n" in mipsr2_decoder()
1895 " dextu %1, %0, 48, 8\n" in mipsr2_decoder()
1896 "7: sb %1, 0(%2)\n" in mipsr2_decoder()
1897 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1898 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1899 " beq $0, %1, 9f\n" in mipsr2_decoder()
1900 " dextu %1, %0, 56, 8\n" in mipsr2_decoder()
1901 "0: sb %1, 0(%2)\n" in mipsr2_decoder()
1903 " dext %1, %0, 0, 8\n" in mipsr2_decoder()
1904 "1: sb %1, 0(%2)\n" in mipsr2_decoder()
1905 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1906 " beq $0, %1, 9f\n" in mipsr2_decoder()
1907 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1908 " dext %1, %0, 8, 8\n" in mipsr2_decoder()
1909 "2: sb %1, 0(%2)\n" in mipsr2_decoder()
1910 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1911 " beq $0, %1, 9f\n" in mipsr2_decoder()
1912 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1913 " dext %1, %0, 16, 8\n" in mipsr2_decoder()
1914 "3: sb %1, 0(%2)\n" in mipsr2_decoder()
1915 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1916 " beq $0, %1, 9f\n" in mipsr2_decoder()
1917 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1918 " dext %1, %0, 24, 8\n" in mipsr2_decoder()
1919 "4: sb %1, 0(%2)\n" in mipsr2_decoder()
1920 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1921 " beq $0, %1, 9f\n" in mipsr2_decoder()
1922 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1923 " dextu %1, %0, 32, 8\n" in mipsr2_decoder()
1924 "5: sb %1, 0(%2)\n" in mipsr2_decoder()
1925 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1926 " beq $0, %1, 9f\n" in mipsr2_decoder()
1927 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1928 " dextu %1, %0, 40, 8\n" in mipsr2_decoder()
1929 "6: sb %1, 0(%2)\n" in mipsr2_decoder()
1930 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1931 " beq $0, %1, 9f\n" in mipsr2_decoder()
1932 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1933 " dextu %1, %0, 48, 8\n" in mipsr2_decoder()
1934 "7: sb %1, 0(%2)\n" in mipsr2_decoder()
1935 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1936 " beq $0, %1, 9f\n" in mipsr2_decoder()
1937 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1938 " dextu %1, %0, 56, 8\n" in mipsr2_decoder()
1939 "0: sb %1, 0(%2)\n" in mipsr2_decoder()
1949 STR(PTR_WD) " 2b,8b\n" in mipsr2_decoder()
1955 STR(PTR_WD) " 0b,8b\n" in mipsr2_decoder()
1967 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
1968 if (vaddr & 0x3) { in mipsr2_decoder()
1969 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
1974 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
2001 "ll %0, 0(%2)\n" in mipsr2_decoder()
2002 "2:\n" in mipsr2_decoder()
2007 "j 2b\n" in mipsr2_decoder()
2017 regs->regs[MIPSInst_RT(inst)] = res; in mipsr2_decoder()
2023 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
2024 if (vaddr & 0x3) { in mipsr2_decoder()
2025 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
2030 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
2055 res = regs->regs[MIPSInst_RT(inst)]; in mipsr2_decoder()
2059 "sc %0, 0(%2)\n" in mipsr2_decoder()
2060 "2:\n" in mipsr2_decoder()
2065 "j 2b\n" in mipsr2_decoder()
2074 regs->regs[MIPSInst_RT(inst)] = res; in mipsr2_decoder()
2086 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
2087 if (vaddr & 0x7) { in mipsr2_decoder()
2088 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
2093 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
2120 "lld %0, 0(%2)\n" in mipsr2_decoder()
2121 "2:\n" in mipsr2_decoder()
2126 "j 2b\n" in mipsr2_decoder()
2135 regs->regs[MIPSInst_RT(inst)] = res; in mipsr2_decoder()
2147 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
2148 if (vaddr & 0x7) { in mipsr2_decoder()
2149 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
2154 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
2179 res = regs->regs[MIPSInst_RT(inst)]; in mipsr2_decoder()
2183 "scd %0, 0(%2)\n" in mipsr2_decoder()
2184 "2:\n" in mipsr2_decoder()
2189 "j 2b\n" in mipsr2_decoder()
2198 regs->regs[MIPSInst_RT(inst)] = res; in mipsr2_decoder()
2215 regs->cp0_cause &= ~CAUSEF_BD; in mipsr2_decoder()
2216 err = get_user(inst, (u32 __user *)regs->cp0_epc); in mipsr2_decoder()
2220 if (err < 0) in mipsr2_decoder()
2225 regs->regs[31] = r31; in mipsr2_decoder()
2226 regs->cp0_epc = epc; in mipsr2_decoder()
2231 err = 0; in mipsr2_decoder()
2241 seq_printf(s, "Instruction\tTotal\tBDslot\n------------------------------\n"); in mipsr2_emul_show()
2301 return 0; in mipsr2_emul_show()
2308 __this_cpu_write((mipsr2emustats).movs, 0); in mipsr2_clear_show()
2309 __this_cpu_write((mipsr2bdemustats).movs, 0); in mipsr2_clear_show()
2310 __this_cpu_write((mipsr2emustats).hilo, 0); in mipsr2_clear_show()
2311 __this_cpu_write((mipsr2bdemustats).hilo, 0); in mipsr2_clear_show()
2312 __this_cpu_write((mipsr2emustats).muls, 0); in mipsr2_clear_show()
2313 __this_cpu_write((mipsr2bdemustats).muls, 0); in mipsr2_clear_show()
2314 __this_cpu_write((mipsr2emustats).divs, 0); in mipsr2_clear_show()
2315 __this_cpu_write((mipsr2bdemustats).divs, 0); in mipsr2_clear_show()
2316 __this_cpu_write((mipsr2emustats).dsps, 0); in mipsr2_clear_show()
2317 __this_cpu_write((mipsr2bdemustats).dsps, 0); in mipsr2_clear_show()
2318 __this_cpu_write((mipsr2emustats).bops, 0); in mipsr2_clear_show()
2319 __this_cpu_write((mipsr2bdemustats).bops, 0); in mipsr2_clear_show()
2320 __this_cpu_write((mipsr2emustats).traps, 0); in mipsr2_clear_show()
2321 __this_cpu_write((mipsr2bdemustats).traps, 0); in mipsr2_clear_show()
2322 __this_cpu_write((mipsr2emustats).fpus, 0); in mipsr2_clear_show()
2323 __this_cpu_write((mipsr2bdemustats).fpus, 0); in mipsr2_clear_show()
2324 __this_cpu_write((mipsr2emustats).loads, 0); in mipsr2_clear_show()
2325 __this_cpu_write((mipsr2bdemustats).loads, 0); in mipsr2_clear_show()
2326 __this_cpu_write((mipsr2emustats).stores, 0); in mipsr2_clear_show()
2327 __this_cpu_write((mipsr2bdemustats).stores, 0); in mipsr2_clear_show()
2328 __this_cpu_write((mipsr2emustats).llsc, 0); in mipsr2_clear_show()
2329 __this_cpu_write((mipsr2bdemustats).llsc, 0); in mipsr2_clear_show()
2330 __this_cpu_write((mipsr2emustats).dsemul, 0); in mipsr2_clear_show()
2331 __this_cpu_write((mipsr2bdemustats).dsemul, 0); in mipsr2_clear_show()
2332 __this_cpu_write((mipsr2bremustats).jrs, 0); in mipsr2_clear_show()
2333 __this_cpu_write((mipsr2bremustats).bltzl, 0); in mipsr2_clear_show()
2334 __this_cpu_write((mipsr2bremustats).bgezl, 0); in mipsr2_clear_show()
2335 __this_cpu_write((mipsr2bremustats).bltzll, 0); in mipsr2_clear_show()
2336 __this_cpu_write((mipsr2bremustats).bgezll, 0); in mipsr2_clear_show()
2337 __this_cpu_write((mipsr2bremustats).bltzall, 0); in mipsr2_clear_show()
2338 __this_cpu_write((mipsr2bremustats).bgezall, 0); in mipsr2_clear_show()
2339 __this_cpu_write((mipsr2bremustats).bltzal, 0); in mipsr2_clear_show()
2340 __this_cpu_write((mipsr2bremustats).bgezal, 0); in mipsr2_clear_show()
2341 __this_cpu_write((mipsr2bremustats).beql, 0); in mipsr2_clear_show()
2342 __this_cpu_write((mipsr2bremustats).bnel, 0); in mipsr2_clear_show()
2343 __this_cpu_write((mipsr2bremustats).blezl, 0); in mipsr2_clear_show()
2344 __this_cpu_write((mipsr2bremustats).bgtzl, 0); in mipsr2_clear_show()
2346 return 0; in mipsr2_clear_show()
2358 return 0; in mipsr2_init_debugfs()