Lines Matching +full:rs +full:-
15 #include <asm/cpu-features.h>
19 #include <asm/mips-r2-to-r6-emul.h>
23 #include "probes-common.h"
32 long epc = regs->cp0_epc; in __isa_exception_epc()
56 /* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */
79 regs->regs[insn.mm_i_format.rt] = in __mm_isBranchInstr()
80 regs->cp0_epc + in __mm_isBranchInstr()
83 *contpc = regs->regs[insn.mm_i_format.rs]; in __mm_isBranchInstr()
92 regs->regs[31] = regs->cp0_epc + in __mm_isBranchInstr()
97 if ((long)regs->regs[insn.mm_i_format.rs] < 0) in __mm_isBranchInstr()
98 *contpc = regs->cp0_epc + in __mm_isBranchInstr()
102 *contpc = regs->cp0_epc + in __mm_isBranchInstr()
108 regs->regs[31] = regs->cp0_epc + in __mm_isBranchInstr()
113 if ((long)regs->regs[insn.mm_i_format.rs] >= 0) in __mm_isBranchInstr()
114 *contpc = regs->cp0_epc + in __mm_isBranchInstr()
118 *contpc = regs->cp0_epc + in __mm_isBranchInstr()
123 if ((long)regs->regs[insn.mm_i_format.rs] <= 0) in __mm_isBranchInstr()
124 *contpc = regs->cp0_epc + in __mm_isBranchInstr()
128 *contpc = regs->cp0_epc + in __mm_isBranchInstr()
133 if ((long)regs->regs[insn.mm_i_format.rs] <= 0) in __mm_isBranchInstr()
134 *contpc = regs->cp0_epc + in __mm_isBranchInstr()
138 *contpc = regs->cp0_epc + in __mm_isBranchInstr()
156 fcr31 = current->thread.fpu.fcr31; in __mm_isBranchInstr()
162 bit = (insn.mm_i_format.rs >> 2); in __mm_isBranchInstr()
166 *contpc = regs->cp0_epc + in __mm_isBranchInstr()
170 *contpc = regs->cp0_epc + in __mm_isBranchInstr()
181 regs->regs[31] = regs->cp0_epc + in __mm_isBranchInstr()
185 *contpc = regs->regs[insn.mm_i_format.rs]; in __mm_isBranchInstr()
190 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] == 0) in __mm_isBranchInstr()
191 *contpc = regs->cp0_epc + in __mm_isBranchInstr()
195 *contpc = regs->cp0_epc + in __mm_isBranchInstr()
199 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0) in __mm_isBranchInstr()
200 *contpc = regs->cp0_epc + in __mm_isBranchInstr()
204 *contpc = regs->cp0_epc + in __mm_isBranchInstr()
208 *contpc = regs->cp0_epc + dec_insn.pc_inc + in __mm_isBranchInstr()
212 if (regs->regs[insn.mm_i_format.rs] == in __mm_isBranchInstr()
213 regs->regs[insn.mm_i_format.rt]) in __mm_isBranchInstr()
214 *contpc = regs->cp0_epc + in __mm_isBranchInstr()
218 *contpc = regs->cp0_epc + in __mm_isBranchInstr()
223 if (regs->regs[insn.mm_i_format.rs] != in __mm_isBranchInstr()
224 regs->regs[insn.mm_i_format.rt]) in __mm_isBranchInstr()
225 *contpc = regs->cp0_epc + in __mm_isBranchInstr()
229 *contpc = regs->cp0_epc + in __mm_isBranchInstr()
233 regs->regs[31] = regs->cp0_epc + in __mm_isBranchInstr()
235 *contpc = regs->cp0_epc + dec_insn.pc_inc; in __mm_isBranchInstr()
242 regs->regs[31] = regs->cp0_epc + in __mm_isBranchInstr()
246 *contpc = regs->cp0_epc + dec_insn.pc_inc; in __mm_isBranchInstr()
273 pc16 = (unsigned short __user *)msk_isa16_mode(regs->cp0_epc); in __microMIPS_compute_return_epc()
276 contpc = regs->cp0_epc + 2; in __microMIPS_compute_return_epc()
283 contpc = regs->cp0_epc + 4; in __microMIPS_compute_return_epc()
305 regs->cp0_epc = contpc; in __microMIPS_compute_return_epc()
311 return -EFAULT; in __microMIPS_compute_return_epc()
328 epc = regs->cp0_epc; in __MIPS16e_compute_return_epc()
334 return -EFAULT; in __MIPS16e_compute_return_epc()
339 regs->cp0_epc += 4; in __MIPS16e_compute_return_epc()
349 return -EFAULT; in __MIPS16e_compute_return_epc()
352 regs->regs[31] = epc + 6; in __MIPS16e_compute_return_epc()
357 * JAL:5 X:1 TARGET[20-16]:5 TARGET[25:21]:5 TARGET[15:0]:16 in __MIPS16e_compute_return_epc()
367 regs->cp0_epc = epc; in __MIPS16e_compute_return_epc()
377 regs->cp0_epc = regs->regs[31]; in __MIPS16e_compute_return_epc()
379 regs->cp0_epc = in __MIPS16e_compute_return_epc()
380 regs->regs[reg16to32[inst.rr.rx]]; in __MIPS16e_compute_return_epc()
384 regs->regs[31] = epc + 2; in __MIPS16e_compute_return_epc()
386 regs->regs[31] = epc + 4; in __MIPS16e_compute_return_epc()
394 * All other cases have no branch delay slot and are 16-bits. in __MIPS16e_compute_return_epc()
397 regs->cp0_epc += 2; in __MIPS16e_compute_return_epc()
403 * __compute_return_epc_for_insn - Computes the return address and do emulate
408 * Return: -EFAULT on error and forces SIGILL, and on success
425 long epc = regs->cp0_epc; in __compute_return_epc_for_insn()
436 regs->regs[insn.r_format.rd] = epc + 8; in __compute_return_epc_for_insn()
441 regs->cp0_epc = regs->regs[insn.r_format.rs]; in __compute_return_epc_for_insn()
458 if ((long)regs->regs[insn.i_format.rs] < 0) { in __compute_return_epc_for_insn()
464 regs->cp0_epc = epc; in __compute_return_epc_for_insn()
472 if ((long)regs->regs[insn.i_format.rs] >= 0) { in __compute_return_epc_for_insn()
478 regs->cp0_epc = epc; in __compute_return_epc_for_insn()
483 if (NO_R6EMU && (insn.i_format.rs || in __compute_return_epc_for_insn()
486 regs->regs[31] = epc + 8; in __compute_return_epc_for_insn()
493 if (!insn.i_format.rs) { in __compute_return_epc_for_insn()
495 * NAL or BLTZAL with rs == 0 in __compute_return_epc_for_insn()
499 regs->cp0_epc += 4 + in __compute_return_epc_for_insn()
503 /* Now do the real thing for non-R6 BLTZAL{,L} */ in __compute_return_epc_for_insn()
504 if ((long)regs->regs[insn.i_format.rs] < 0) { in __compute_return_epc_for_insn()
510 regs->cp0_epc = epc; in __compute_return_epc_for_insn()
515 if (NO_R6EMU && (insn.i_format.rs || in __compute_return_epc_for_insn()
518 regs->regs[31] = epc + 8; in __compute_return_epc_for_insn()
525 if (!insn.i_format.rs) { in __compute_return_epc_for_insn()
527 * BAL or BGEZAL with rs == 0 in __compute_return_epc_for_insn()
531 regs->cp0_epc += 4 + in __compute_return_epc_for_insn()
535 /* Now do the real thing for non-R6 BGEZAL{,L} */ in __compute_return_epc_for_insn()
536 if ((long)regs->regs[insn.i_format.rs] >= 0) { in __compute_return_epc_for_insn()
542 regs->cp0_epc = epc; in __compute_return_epc_for_insn()
555 regs->cp0_epc = epc; in __compute_return_epc_for_insn()
565 regs->regs[31] = regs->cp0_epc + 8; in __compute_return_epc_for_insn()
572 regs->cp0_epc = epc; in __compute_return_epc_for_insn()
574 set_isa16_mode(regs->cp0_epc); in __compute_return_epc_for_insn()
585 if (regs->regs[insn.i_format.rs] == in __compute_return_epc_for_insn()
586 regs->regs[insn.i_format.rt]) { in __compute_return_epc_for_insn()
592 regs->cp0_epc = epc; in __compute_return_epc_for_insn()
600 if (regs->regs[insn.i_format.rs] != in __compute_return_epc_for_insn()
601 regs->regs[insn.i_format.rt]) { in __compute_return_epc_for_insn()
607 regs->cp0_epc = epc; in __compute_return_epc_for_insn()
618 * BLEZ | rs = 0 | rt != 0 == BLEZALC in __compute_return_epc_for_insn()
619 * BLEZ | rs = rt != 0 == BGEZALC in __compute_return_epc_for_insn()
620 * BLEZ | rs != 0 | rt != 0 == BGEUC in __compute_return_epc_for_insn()
621 * BLEZL | rs = 0 | rt != 0 == BLEZC in __compute_return_epc_for_insn()
622 * BLEZL | rs = rt != 0 == BGEZC in __compute_return_epc_for_insn()
623 * BLEZL | rs != 0 | rt != 0 == BGEC in __compute_return_epc_for_insn()
630 ((!insn.i_format.rs && insn.i_format.rt) || in __compute_return_epc_for_insn()
631 (insn.i_format.rs == insn.i_format.rt))) in __compute_return_epc_for_insn()
632 regs->regs[31] = epc + 4; in __compute_return_epc_for_insn()
633 regs->cp0_epc += 8; in __compute_return_epc_for_insn()
637 if ((long)regs->regs[insn.i_format.rs] <= 0) { in __compute_return_epc_for_insn()
643 regs->cp0_epc = epc; in __compute_return_epc_for_insn()
654 * BGTZ | rs = 0 | rt != 0 == BGTZALC in __compute_return_epc_for_insn()
655 * BGTZ | rs = rt != 0 == BLTZALC in __compute_return_epc_for_insn()
656 * BGTZ | rs != 0 | rt != 0 == BLTUC in __compute_return_epc_for_insn()
657 * BGTZL | rs = 0 | rt != 0 == BGTZC in __compute_return_epc_for_insn()
658 * BGTZL | rs = rt != 0 == BLTZC in __compute_return_epc_for_insn()
659 * BGTZL | rs != 0 | rt != 0 == BLTC in __compute_return_epc_for_insn()
666 ((!insn.i_format.rs && insn.i_format.rt) || in __compute_return_epc_for_insn()
667 (insn.i_format.rs == insn.i_format.rt))) in __compute_return_epc_for_insn()
668 regs->regs[31] = epc + 4; in __compute_return_epc_for_insn()
669 regs->cp0_epc += 8; in __compute_return_epc_for_insn()
674 if ((long)regs->regs[insn.i_format.rs] > 0) { in __compute_return_epc_for_insn()
680 regs->cp0_epc = epc; in __compute_return_epc_for_insn()
691 ((insn.i_format.rs == bc1eqz_op) || in __compute_return_epc_for_insn()
692 (insn.i_format.rs == bc1nez_op))) { in __compute_return_epc_for_insn()
696 bit = get_fpr32(¤t->thread.fpu.fpr[reg], 0) & 0x1; in __compute_return_epc_for_insn()
697 if (insn.i_format.rs == bc1eqz_op) in __compute_return_epc_for_insn()
705 regs->cp0_epc = epc; in __compute_return_epc_for_insn()
714 fcr31 = current->thread.fpu.fcr31; in __compute_return_epc_for_insn()
730 regs->cp0_epc = epc; in __compute_return_epc_for_insn()
742 regs->cp0_epc = epc; in __compute_return_epc_for_insn()
752 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) in __compute_return_epc_for_insn()
757 regs->cp0_epc = epc; in __compute_return_epc_for_insn()
760 if ((regs->regs[insn.i_format.rs] & in __compute_return_epc_for_insn()
765 regs->cp0_epc = epc; in __compute_return_epc_for_insn()
768 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) in __compute_return_epc_for_insn()
772 regs->cp0_epc = epc; in __compute_return_epc_for_insn()
775 if (regs->regs[insn.i_format.rs] & in __compute_return_epc_for_insn()
780 regs->cp0_epc = epc; in __compute_return_epc_for_insn()
787 regs->cp0_epc += 8; in __compute_return_epc_for_insn()
793 regs->regs[31] = epc + 4; in __compute_return_epc_for_insn()
795 regs->cp0_epc = epc; in __compute_return_epc_for_insn()
801 regs->cp0_epc += 8; in __compute_return_epc_for_insn()
807 if (!insn.i_format.rs) { in __compute_return_epc_for_insn()
809 regs->regs[31] = epc + 4; in __compute_return_epc_for_insn()
811 regs->cp0_epc += 8; in __compute_return_epc_for_insn()
823 if (insn.i_format.rt && !insn.i_format.rs) in __compute_return_epc_for_insn()
824 regs->regs[31] = epc + 4; in __compute_return_epc_for_insn()
825 regs->cp0_epc += 8; in __compute_return_epc_for_insn()
832 pr_debug("%s: DSP branch but not DSP ASE - sending SIGILL.\n", in __compute_return_epc_for_insn()
833 current->comm); in __compute_return_epc_for_insn()
835 return -EFAULT; in __compute_return_epc_for_insn()
837 pr_debug("%s: R2 branch but r2-to-r6 emulator is not present - sending SIGILL.\n", in __compute_return_epc_for_insn()
838 current->comm); in __compute_return_epc_for_insn()
840 return -EFAULT; in __compute_return_epc_for_insn()
842 pr_debug("%s: R6 branch but no MIPSr6 ISA support - sending SIGILL.\n", in __compute_return_epc_for_insn()
843 current->comm); in __compute_return_epc_for_insn()
845 return -EFAULT; in __compute_return_epc_for_insn()
855 epc = regs->cp0_epc; in __compute_return_epc()
865 return -EFAULT; in __compute_return_epc()
871 printk("%s: unaligned epc - sending SIGBUS.\n", current->comm); in __compute_return_epc()
873 return -EFAULT; in __compute_return_epc()
889 * blez[l] and bgtz[l] opcodes with non-zero rt in __insn_is_compact_branch()