Lines Matching +full:0 +full:- +full:5

1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
69 	clz_op = 0x20, clo_op,
70 	dclz_op = 0x24, dclo_op,
71 	sdbpp_op = 0x3f
80 	yield_op  = 0x09, lx_op     = 0x0a,
81 	lwle_op   = 0x19, lwre_op   = 0x1a,
82 	cachee_op = 0x1b, sbe_op    = 0x1c,
83 	she_op    = 0x1d, sce_op    = 0x1e,
84 	swe_op    = 0x1f, bshfl_op  = 0x20,
85 	swle_op   = 0x21, swre_op   = 0x22,
86 	prefe_op  = 0x23, dbshfl_op = 0x24,
87 	cache6_op = 0x25, sc6_op    = 0x26,
88 	scd6_op   = 0x27, lbue_op   = 0x28,
89 	lhue_op   = 0x29, lbe_op    = 0x2c,
90 	lhe_op    = 0x2d, lle_op    = 0x2e,
91 	lwe_op    = 0x2f, pref6_op  = 0x35,
92 	ll6_op    = 0x36, lld6_op   = 0x37,
93 	rdhwr_op  = 0x3b
97  * Bits 10-6 minor opcode for r6 spec mult/div encodings
100 	mult_mult_op = 0x0,
101 	mult_mul_op = 0x2,
102 	mult_muh_op = 0x3,
105 	multu_multu_op = 0x0,
106 	multu_mulu_op = 0x2,
107 	multu_muhu_op = 0x3,
110 	div_div_op = 0x0,
111 	div_div6_op = 0x2,
112 	div_mod_op = 0x3,
115 	divu_divu_op = 0x0,
116 	divu_divu6_op = 0x2,
117 	divu_modu_op = 0x3,
120 	dmult_dmult_op = 0x0,
121 	dmult_dmul_op = 0x2,
122 	dmult_dmuh_op = 0x3,
125 	dmultu_dmultu_op = 0x0,
126 	dmultu_dmulu_op = 0x2,
127 	dmultu_dmuhu_op = 0x3,
130 	ddiv_ddiv_op = 0x0,
131 	ddiv_ddiv6_op = 0x2,
132 	ddiv_dmod_op = 0x3,
135 	ddivu_ddivu_op = 0x0,
136 	ddivu_ddivu6_op = 0x2,
137 	ddivu_dmodu_op = 0x3,
158 	mfc_op	      = 0x00, dmfc_op	    = 0x01,
159 	cfc_op	      = 0x02, mfhc0_op	    = 0x02,
160 	mfhc_op       = 0x03, mtc_op	    = 0x04,
161 	dmtc_op	      = 0x05, ctc_op	    = 0x06,
162 	mthc0_op      = 0x06, mthc_op	    = 0x07,
163 	bc_op	      = 0x08, bc1eqz_op     = 0x09,
164 	mfmc0_op      = 0x0b, bc1nez_op     = 0x0d,
165 	wrpgpr_op     = 0x0e, cop_op	    = 0x10,
166 	copm_op	      = 0x18
180 	tlbr_op	      = 0x01, tlbwi_op	    = 0x02,
181 	tlbwr_op      = 0x06, tlbp_op	    = 0x08,
182 	rfe_op	      = 0x10, eret_op	    = 0x18,
183 	wait_op       = 0x20, hypcall_op    = 0x28
190 	tlbr1_op      = 0x01, tlbw_op	    = 0x02,
191 	tlbp1_op      = 0x08, dctr_op	    = 0x09,
192 	dctw_op	      = 0x0a
207 	fadd_op	     =	0x00, fsub_op	   =  0x01,
208 	fmul_op	     =	0x02, fdiv_op	   =  0x03,
209 	fsqrt_op     =	0x04, fabs_op	   =  0x05,
210 	fmov_op	     =	0x06, fneg_op	   =  0x07,
211 	froundl_op   =	0x08, ftruncl_op   =  0x09,
212 	fceill_op    =	0x0a, ffloorl_op   =  0x0b,
213 	fround_op    =	0x0c, ftrunc_op	   =  0x0d,
214 	fceil_op     =	0x0e, ffloor_op	   =  0x0f,
215 	fsel_op      =  0x10,
216 	fmovc_op     =	0x11, fmovz_op	   =  0x12,
217 	fmovn_op     =	0x13, fseleqz_op   =  0x14,
218 	frecip_op    =  0x15, frsqrt_op    =  0x16,
219 	fselnez_op   =  0x17, fmaddf_op    =  0x18,
220 	fmsubf_op    =  0x19, frint_op     =  0x1a,
221 	fclass_op    =  0x1b, fmin_op      =  0x1c,
222 	fmina_op     =  0x1d, fmax_op      =  0x1e,
223 	fmaxa_op     =  0x1f, fcvts_op     =  0x20,
224 	fcvtd_op     =	0x21, fcvte_op	   =  0x22,
225 	fcvtw_op     =	0x24, fcvtl_op	   =  0x25,
226 	fcmp_op	     =	0x30
233 	lwxc1_op     =	0x00, ldxc1_op	   =  0x01,
234 	swxc1_op     =  0x08, sdxc1_op	   =  0x09,
235 	pfetch_op    =	0x0f, madd_s_op	   =  0x20,
236 	madd_d_op    =	0x21, madd_e_op	   =  0x22,
237 	msub_s_op    =	0x28, msub_d_op	   =  0x29,
238 	msub_e_op    =	0x2a, nmadd_s_op   =  0x30,
239 	nmadd_d_op   =	0x31, nmadd_e_op   =  0x32,
240 	nmsub_s_op   =	0x38, nmsub_d_op   =  0x39,
241 	nmsub_e_op   =	0x3a
248 	madd_fp_op	= 0x08, msub_fp_op	= 0x0a,
249 	nmadd_fp_op	= 0x0c, nmsub_fp_op	= 0x0e
253  * func field for page table walker (Loongson-3).
256 	lwdir_op = 0x00,
257 	lwpte_op = 0x01,
258 	lddir_op = 0x02,
259 	ldpte_op = 0x03,
266 	lwx_op	= 0x00,
267 	lhx_op	= 0x04,
268 	lbux_op = 0x06,
269 	ldx_op	= 0x08,
270 	lwux_op = 0x10,
271 	lhux_op = 0x14,
272 	lbx_op	= 0x16,
279 	wsbh_op = 0x2,
280 	seb_op  = 0x10,
281 	seh_op  = 0x18,
288 	dsbh_op = 0x2,
289 	dshd_op = 0x5,
296 	msa_elm_op = 0x19,
303 	msa_ctc_op = 0x3e,
304 	msa_cfc_op = 0x7e,
319 	msa_fmt_b = 0,
366 	mm_sll32_op = 0x000,
367 	mm_ins_op = 0x00c,
368 	mm_sllv32_op = 0x010,
369 	mm_ext_op = 0x02c,
370 	mm_pool32axf_op = 0x03c,
371 	mm_srl32_op = 0x040,
372 	mm_srlv32_op = 0x050,
373 	mm_sra_op = 0x080,
374 	mm_srav_op = 0x090,
375 	mm_rotr_op = 0x0c0,
376 	mm_lwxs_op = 0x118,
377 	mm_addu32_op = 0x150,
378 	mm_subu32_op = 0x1d0,
379 	mm_wsbh_op = 0x1ec,
380 	mm_mul_op = 0x210,
381 	mm_and_op = 0x250,
382 	mm_or32_op = 0x290,
383 	mm_xor32_op = 0x310,
384 	mm_slt_op = 0x350,
385 	mm_sltu_op = 0x390,
392 	mm_lwc2_func = 0x0,
393 	mm_lwp_func = 0x1,
394 	mm_ldc2_func = 0x2,
395 	mm_ldp_func = 0x4,
396 	mm_lwm32_func = 0x5,
397 	mm_cache_func = 0x6,
398 	mm_ldm_func = 0x7,
399 	mm_swc2_func = 0x8,
400 	mm_swp_func = 0x9,
401 	mm_sdc2_func = 0xa,
402 	mm_sdp_func = 0xc,
403 	mm_swm32_func = 0xd,
404 	mm_sdm_func = 0xf,
411 	mm_pref_func = 0x2,
412 	mm_ll_func = 0x3,
413 	mm_swr_func = 0x9,
414 	mm_sc_func = 0xb,
415 	mm_lwu_func = 0xe,
422 	mm_mfc0_op = 0x003,
423 	mm_mtc0_op = 0x00b,
424 	mm_tlbp_op = 0x00d,
425 	mm_mfhi32_op = 0x035,
426 	mm_jalr_op = 0x03c,
427 	mm_tlbr_op = 0x04d,
428 	mm_mflo32_op = 0x075,
429 	mm_jalrhb_op = 0x07c,
430 	mm_tlbwi_op = 0x08d,
431 	mm_mthi32_op = 0x0b5,
432 	mm_tlbwr_op = 0x0cd,
433 	mm_mtlo32_op = 0x0f5,
434 	mm_di_op = 0x11d,
435 	mm_jalrs_op = 0x13c,
436 	mm_jalrshb_op = 0x17c,
437 	mm_sync_op = 0x1ad,
438 	mm_syscall_op = 0x22d,
439 	mm_wait_op = 0x24d,
440 	mm_eret_op = 0x3cd,
441 	mm_divu_op = 0x5dc,
448 	mm_32f_00_op = 0x00,
449 	mm_32f_01_op = 0x01,
450 	mm_32f_02_op = 0x02,
451 	mm_32f_10_op = 0x08,
452 	mm_32f_11_op = 0x09,
453 	mm_32f_12_op = 0x0a,
454 	mm_32f_20_op = 0x10,
455 	mm_32f_30_op = 0x18,
456 	mm_32f_40_op = 0x20,
457 	mm_32f_41_op = 0x21,
458 	mm_32f_42_op = 0x22,
459 	mm_32f_50_op = 0x28,
460 	mm_32f_51_op = 0x29,
461 	mm_32f_52_op = 0x2a,
462 	mm_32f_60_op = 0x30,
463 	mm_32f_70_op = 0x38,
464 	mm_32f_73_op = 0x3b,
465 	mm_32f_74_op = 0x3c,
472 	mm_lwxc1_op = 0x1,
481 	mm_lwxc1_func = 0x048,
482 	mm_swxc1_func = 0x088,
483 	mm_ldxc1_func = 0x0c8,
484 	mm_sdxc1_func = 0x108,
517 	mm_fmov0_op = 0x01,
518 	mm_fcvtl_op = 0x04,
519 	mm_movf0_op = 0x05,
520 	mm_frsqrt_op = 0x08,
521 	mm_ffloorl_op = 0x0c,
522 	mm_fabs0_op = 0x0d,
523 	mm_fcvtw_op = 0x24,
524 	mm_movt0_op = 0x25,
525 	mm_fsqrt_op = 0x28,
526 	mm_ffloorw_op = 0x2c,
527 	mm_fneg0_op = 0x2d,
528 	mm_cfc1_op = 0x40,
529 	mm_frecip_op = 0x48,
530 	mm_fceill_op = 0x4c,
531 	mm_fcvtd0_op = 0x4d,
532 	mm_ctc1_op = 0x60,
533 	mm_fceilw_op = 0x6c,
534 	mm_fcvts0_op = 0x6d,
535 	mm_mfc1_op = 0x80,
536 	mm_fmov1_op = 0x81,
537 	mm_movf1_op = 0x85,
538 	mm_ftruncl_op = 0x8c,
539 	mm_fabs1_op = 0x8d,
540 	mm_mtc1_op = 0xa0,
541 	mm_movt1_op = 0xa5,
542 	mm_ftruncw_op = 0xac,
543 	mm_fneg1_op = 0xad,
544 	mm_mfhc1_op = 0xc0,
545 	mm_froundl_op = 0xcc,
546 	mm_fcvtd1_op = 0xcd,
547 	mm_mthc1_op = 0xe0,
548 	mm_froundw_op = 0xec,
549 	mm_fcvts1_op = 0xed,
556 	mm_32s_elm_op = 0x16,
563 	mm_lwm16_op = 0x04,
564 	mm_swm16_op = 0x05,
565 	mm_jr16_op = 0x0c,
566 	mm_jrc_op = 0x0d,
567 	mm_jalr16_op = 0x0e,
568 	mm_jalrs16_op = 0x0f,
569 	mm_jraddiusp_op = 0x18,
624 #define MM_NOP16	0x0c00
634 	__BITFIELD_FIELD(unsigned int rs : 5,
635 	__BITFIELD_FIELD(unsigned int rt : 5,
642 	__BITFIELD_FIELD(unsigned int rs : 5,
643 	__BITFIELD_FIELD(unsigned int rt : 5,
650 	__BITFIELD_FIELD(unsigned int rs : 5,
659 	__BITFIELD_FIELD(unsigned int rs : 5,
660 	__BITFIELD_FIELD(unsigned int rt : 5,
661 	__BITFIELD_FIELD(unsigned int rd : 5,
662 	__BITFIELD_FIELD(unsigned int re : 5,
669 	__BITFIELD_FIELD(unsigned int rs : 5,
670 	__BITFIELD_FIELD(unsigned int rt : 5,
671 	__BITFIELD_FIELD(unsigned int rd : 5,
679 	__BITFIELD_FIELD(unsigned int rs : 5,
680 	__BITFIELD_FIELD(unsigned int rt : 5,
681 	__BITFIELD_FIELD(unsigned int rd : 5,
682 	__BITFIELD_FIELD(unsigned int re : 5,
699 	__BITFIELD_FIELD(unsigned int rs : 5,
700 	__BITFIELD_FIELD(unsigned int rt : 5,
701 	__BITFIELD_FIELD(unsigned int rd : 5,
702 	__BITFIELD_FIELD(unsigned int re : 5,
711 	__BITFIELD_FIELD(unsigned int rt : 5,
712 	__BITFIELD_FIELD(unsigned int rd : 5,
713 	__BITFIELD_FIELD(unsigned int re : 5,
720 	__BITFIELD_FIELD(unsigned int fr : 5,
721 	__BITFIELD_FIELD(unsigned int ft : 5,
722 	__BITFIELD_FIELD(unsigned int fs : 5,
723 	__BITFIELD_FIELD(unsigned int fd : 5,
736 struct ps_format {			/* MIPS-3D / paired single format */
738 	__BITFIELD_FIELD(unsigned int rs : 5,
739 	__BITFIELD_FIELD(unsigned int ft : 5,
740 	__BITFIELD_FIELD(unsigned int fs : 5,
741 	__BITFIELD_FIELD(unsigned int fd : 5,
750 	__BITFIELD_FIELD(unsigned int vt : 5,
751 	__BITFIELD_FIELD(unsigned int vs : 5,
752 	__BITFIELD_FIELD(unsigned int vd : 5,
760 	__BITFIELD_FIELD(unsigned int rs : 5,
761 	__BITFIELD_FIELD(unsigned int wd : 5,
769 	__BITFIELD_FIELD(unsigned int base : 5,
770 	__BITFIELD_FIELD(unsigned int index : 5,
771 	__BITFIELD_FIELD(unsigned int rd : 5,
772 	__BITFIELD_FIELD(unsigned int op : 5,
779 	__BITFIELD_FIELD(unsigned int rs:5,
780 	__BITFIELD_FIELD(unsigned int rt:5,
787  * microMIPS instruction formats (32-bit length)
791  *	if it is MIPS32 instruction re-encoded for use in the microMIPS ASE.
795 	__BITFIELD_FIELD(unsigned int bc : 5,
804 	__BITFIELD_FIELD(unsigned int fmt : 5,
805 	__BITFIELD_FIELD(unsigned int ft : 5,
806 	__BITFIELD_FIELD(unsigned int fs : 5,
807 	__BITFIELD_FIELD(unsigned int fd : 5,
814 	__BITFIELD_FIELD(unsigned int ft : 5,
815 	__BITFIELD_FIELD(unsigned int fs : 5,
816 	__BITFIELD_FIELD(unsigned int fd : 5,
825 	__BITFIELD_FIELD(unsigned int op : 5,
826 	__BITFIELD_FIELD(unsigned int rt : 5,
827 	__BITFIELD_FIELD(unsigned int fs : 5,
828 	__BITFIELD_FIELD(unsigned int fd : 5,
835 	__BITFIELD_FIELD(unsigned int rt : 5,
836 	__BITFIELD_FIELD(unsigned int fs : 5,
845 	__BITFIELD_FIELD(unsigned int fd : 5,
846 	__BITFIELD_FIELD(unsigned int fs : 5,
857 	__BITFIELD_FIELD(unsigned int rt : 5,
858 	__BITFIELD_FIELD(unsigned int fs : 5,
867 	__BITFIELD_FIELD(unsigned int rt : 5,
868 	__BITFIELD_FIELD(unsigned int fs : 5,
878 	__BITFIELD_FIELD(unsigned int index : 5,
879 	__BITFIELD_FIELD(unsigned int base : 5,
880 	__BITFIELD_FIELD(unsigned int fd : 5,
881 	__BITFIELD_FIELD(unsigned int op : 5,
888 	__BITFIELD_FIELD(unsigned int fr : 5,
889 	__BITFIELD_FIELD(unsigned int ft : 5,
890 	__BITFIELD_FIELD(unsigned int fs : 5,
891 	__BITFIELD_FIELD(unsigned int fd : 5,
898 	__BITFIELD_FIELD(unsigned int ft : 5,
899 	__BITFIELD_FIELD(unsigned int fs : 5,
900 	__BITFIELD_FIELD(unsigned int fd : 5,
901 	__BITFIELD_FIELD(unsigned int fr : 5,
908 	__BITFIELD_FIELD(unsigned int rt : 5,
909 	__BITFIELD_FIELD(unsigned int rs : 5,
914 struct mm_m_format {		/* Multi-word load/store format (microMIPS) */
916 	__BITFIELD_FIELD(unsigned int rd : 5,
917 	__BITFIELD_FIELD(unsigned int base : 5,
925 	__BITFIELD_FIELD(unsigned int index : 5,
926 	__BITFIELD_FIELD(unsigned int base : 5,
927 	__BITFIELD_FIELD(unsigned int rd : 5,
940  * microMIPS instruction formats (16-bit length)
957 struct mm16_m_format {		/* Multi-word load/store format */
985 	__BITFIELD_FIELD(unsigned int rt : 5,
986 	__BITFIELD_FIELD(unsigned int imm : 5,
992  * Loongson-3 overridden COP2 instruction formats (32-bit length)
994 struct loongson3_lswc2_format {	/* Loongson-3 overridden lwc2/swc2 Load/Store format */
996 	__BITFIELD_FIELD(unsigned int base : 5,
997 	__BITFIELD_FIELD(unsigned int rt : 5,
1001 	__BITFIELD_FIELD(unsigned int rq : 5,
1005 struct loongson3_lsdc2_format {	/* Loongson-3 overridden ldc2/sdc2 Load/Store format */
1007 	__BITFIELD_FIELD(unsigned int base : 5,
1008 	__BITFIELD_FIELD(unsigned int rt : 5,
1009 	__BITFIELD_FIELD(unsigned int index : 5,
1015 struct loongson3_lscsr_format {	/* Loongson-3 CPUCFG&CSR read/write format */
1017 	__BITFIELD_FIELD(unsigned int rs : 5,
1018 	__BITFIELD_FIELD(unsigned int fr : 5,
1019 	__BITFIELD_FIELD(unsigned int rd : 5,
1020 	__BITFIELD_FIELD(unsigned int fd : 5,
1026  * MIPS16e instruction formats (16-bit length)
1029 	__BITFIELD_FIELD(unsigned int opcode : 5,
1034 	__BITFIELD_FIELD(unsigned int func : 5,
1039 	__BITFIELD_FIELD(unsigned int opcode : 5,
1041 	__BITFIELD_FIELD(unsigned int imm20_16 : 5,
1042 	__BITFIELD_FIELD(signed int imm25_21 : 5,
1047 	__BITFIELD_FIELD(unsigned int opcode : 5,
1054 	__BITFIELD_FIELD(unsigned int opcode : 5,
1057 	__BITFIELD_FIELD(unsigned int imm : 5,
1062 	__BITFIELD_FIELD(unsigned int opcode : 5,
1069 	__BITFIELD_FIELD(unsigned int opcode : 5,
1072 	__BITFIELD_FIELD(unsigned int imm : 5,
1077 	__BITFIELD_FIELD(unsigned int opcode : 5,