Lines Matching full:sync
6 * sync types are defined by the MIPS64 Instruction Set documentation in Volume
43 * No sync instruction at all; used to allow code to nullify the effect of the
49 * A full completion barrier; all memory accesses appearing prior to this sync
51 * appearing after this sync instruction in program order.
56 * For now we use a full completion barrier to implement all sync types, until
78 * A GINV sync is a little different; it doesn't relate directly to loads or
82 * has been performed by all coherent CPUs, we must issue a sync instruction of
88 /* Trivial; indicate that we always need this sync instruction. */
92 * Indicate that we need this sync instruction only on systems with weakly
103 * Indicate that we need this sync instruction only on systems where LL/SC
123 * In order to avoid this we need to place a memory barrier (ie. a SYNC
134 * In order to avoid this we need a memory barrier (ie. a SYNC instruction)
157 * sync instructions should be emitted twice.
168 * The main event. Here we actually emit a sync instruction of a given type, if
172 * here that would allow us to opportunistically remove some sync instructions
182 sync _type; \