Lines Matching +full:pio +full:- +full:transfer
40 u32 _unused0[0x1000/4 - 2]; /* padding */
48 #define HPC3_PDMACTRL_SEL 0x00000002 /* little endian transfer */
51 #define HPC3_PDMACTRL_ACT 0x00000010 /* start dma transfer */
54 #define HPC3_PDMACTRL_HW 0x0000ff00 /* DMA High-water mark */
58 u32 _unused1[0x1000/4 - 1]; /* padding */
65 u32 _unused0[0x1000/4 - 2]; /* padding */
67 #define HPC3_SBCD_BCNTMSK 0x00003fff /* bytes to transfer from/to memory */
77 #define HPC3_SCTRL_AMASK 0x20 /* DMA active inhibits PIO */
89 #define HPC3_SDCFG_HW 0x01000 /* Enable 16-bit halfword DMA accesses to scsi */
95 volatile u32 pconfig; /* PIO configuration register */
100 #define HPC3_SPCFG_HW 0x1000 /* Enable 16-bit halfword PIO accesses to scsi */
101 #define HPC3_SPCFG_SWAP 0x2000 /* Byte swap all PIO accesses */
102 #define HPC3_SPCFG_EPAR 0x4000 /* Enable parity checking for PIO */
103 #define HPC3_SPCFG_FUJI 0x8000 /* Fujitsu scsi controller mode for faster dma/pio */
105 u32 _unused1[0x1000/4 - 6]; /* padding */
113 u32 _unused0[0x1000/4 - 2]; /* padding */
124 #define HPC3_ERXCTRL_ACTIVE 0x00000200 /* Tells if DMA transfer is in progress */
125 #define HPC3_ERXCTRL_AMASK 0x00000400 /* Tells if ACTIVE inhibits PIO's to hpc3 */
137 #define HPC3_EDCFG_D1 0x0000f /* Cycles to spend in D1 state for PIO */
138 #define HPC3_EDCFG_D2 0x000f0 /* Cycles to spend in D2 state for PIO */
139 #define HPC3_EDCFG_D3 0x00f00 /* Cycles to spend in D3 state for PIO */
146 volatile u32 pconfig; /* PIO configuration register */
147 #define HPC3_EPCFG_P1 0x000f /* Cycles to spend in P1 state for PIO */
148 #define HPC3_EPCFG_P2 0x00f0 /* Cycles to spend in P2 state for PIO */
149 #define HPC3_EPCFG_P3 0x0f00 /* Cycles to spend in P3 state for PIO */
152 u32 _unused2[0x1000/4 - 8]; /* padding */
157 u32 _unused3[0x1000/4 - 2]; /* padding */
171 #define HPC3_ETXCTRL_AMASK 0x00000400 /* Indicates ACTIVE inhibits PIO's */
175 u32 _unused4[0x1000/4 - 4]; /* padding */
189 * via PIO accesses. Under normal operation we never stick
198 * you it was a peculiar bug. ;-)
201 #define HPC3_ISTAT_PBIMASK 0x0ff /* irq bits for pbus devs 0 --> 7 */
219 #define HPC3_BESTAT_CTYPE 0x00100 /* Bus cycle type, 0=PIO 1=DMA */
223 u32 _unused1[0x14000/4 - 5]; /* padding */
225 /* Now direct PIO per-HPC3 peripheral access to external regs. */
233 /* Per-peripheral device external registers and DMA/PIO control. */
254 /* Enable 16-bit DMA access mode */
284 /* Enable 16-bit PIO accesses */
293 u32 _unused5[0x0800/4 - 1];
297 u32 _unused6[0x0800/4 - 1];
301 u32 _unused7[0x1000/4 - 1];
304 volatile u32 bbram[8192-50-14]; /* Battery backed ram */