Lines Matching +full:data +full:- +full:enable +full:- +full:active
20 u32 pbuf; /* physical address of data buffer */
40 u32 _unused0[0x1000/4 - 2]; /* padding */
46 #define HPC3_PDMACTRL_ISACT 0x00000002 /* channel active */
50 #define HPC3_PDMACTRL_FLSH 0x00000008 /* enable flush for receive DMA */
52 #define HPC3_PDMACTRL_LD 0x00000020 /* load enable for ACT */
54 #define HPC3_PDMACTRL_HW 0x0000ff00 /* DMA High-water mark */
58 u32 _unused1[0x1000/4 - 1]; /* padding */
65 u32 _unused0[0x1000/4 - 2]; /* padding */
76 #define HPC3_SCTRL_ACTIVE 0x10 /* SCSI DMA channel is active */
77 #define HPC3_SCTRL_AMASK 0x20 /* DMA active inhibits PIO */
84 #define HPC3_SDCFG_HCLK 0x00001 /* Enable DMA half clock mode */
89 #define HPC3_SDCFG_HW 0x01000 /* Enable 16-bit halfword DMA accesses to scsi */
91 #define HPC3_SDCFG_EPAR 0x04000 /* Enable parity checking for DMA */
100 #define HPC3_SPCFG_HW 0x1000 /* Enable 16-bit halfword PIO accesses to scsi */
102 #define HPC3_SPCFG_EPAR 0x4000 /* Enable parity checking for PIO */
105 u32 _unused1[0x1000/4 - 6]; /* padding */
113 u32 _unused0[0x1000/4 - 2]; /* padding */
125 #define HPC3_ERXCTRL_AMASK 0x00000400 /* Tells if ACTIVE inhibits PIO's to hpc3 */
134 #define HPC3_ERST_LBACK 0x4 /* Enable diagnostic loopback mode of Seeq8003 */
140 #define HPC3_EDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */
142 #define HPC3_EDCFG_FEOP 0x04000 /* Bad packet marker timeout enable */
143 #define HPC3_EDCFG_FIRQ 0x08000 /* Another bad packet timeout enable */
152 u32 _unused2[0x1000/4 - 8]; /* padding */
157 u32 _unused3[0x1000/4 - 2]; /* padding */
170 #define HPC3_ETXCTRL_ACTIVE 0x00000200 /* DMA tx channel is active */
171 #define HPC3_ETXCTRL_AMASK 0x00000400 /* Indicates ACTIVE inhibits PIO's */
175 u32 _unused4[0x1000/4 - 4]; /* padding */
198 * you it was a peculiar bug. ;-)
201 #define HPC3_ISTAT_PBIMASK 0x0ff /* irq bits for pbus devs 0 --> 7 */
206 #define HPC3_GIOMISC_ERTIME 0x1 /* Enable external timer real time. */
209 u32 eeprom; /* EEPROM data reg. */
210 #define HPC3_EEPROM_EPROT 0x01 /* Protect register enable */
213 #define HPC3_EEPROM_DATO 0x08 /* Data out */
214 #define HPC3_EEPROM_DATI 0x10 /* Data in */
223 u32 _unused1[0x14000/4 - 5]; /* padding */
225 /* Now direct PIO per-HPC3 peripheral access to external regs. */
233 /* Per-peripheral device external registers and DMA/PIO control. */
254 /* Enable 16-bit DMA access mode */
284 /* Enable 16-bit PIO accesses */
290 volatile u32 pbus_promwe; /* PROM write enable register */
291 #define HPC3_PROM_WENAB 0x1 /* Enable writes to the PROM */
293 u32 _unused5[0x0800/4 - 1];
297 u32 _unused6[0x0800/4 - 1];
301 u32 _unused7[0x1000/4 - 1];
304 volatile u32 bbram[8192-50-14]; /* Battery backed ram */