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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 # error Please include asm/mips-cps.h rather than asm/mips-cm.h
21 /* The base address of the CM L2-only sync region */
25 * __mips_cm_phys_base - retrieve the physical base address of the CM
37 * mips_cm_is64 - determine CM register width
40 * introducing 64 bit GCRs and all prior CM versions having 32 bit GCRs.
41 * However we may run a kernel built for MIPS32 on a system with 64 bit GCRs,
42 * or vice-versa. This variable indicates the width of the memory accesses
46 * It's set to 0 for 32-bit accesses and 1 for 64-bit accesses.
51 * mips_cm_error_report - Report CM cache errors
60 * mips_cm_probe - probe for a Coherence Manager
63 * is successfully detected, else -errno.
70 return -ENODEV; in mips_cm_probe()
75 * mips_cm_present - determine whether a Coherence Manager is present
89 * mips_cm_has_l2sync - determine whether an L2-only sync region is present
91 * Returns true if the system implements an L2-only sync region, else false.
111 /* Size of the L2-only sync region */
130 /* GCR_CONFIG - Information about the system */
131 GCR_ACCESSOR_RO(64, 0x000, config)
138 /* GCR_BASE - Base address of the Global Configuration Registers (GCRs) */
139 GCR_ACCESSOR_RW(64, 0x008, base)
147 /* GCR_ACCESS - Controls core/IOCU access to GCRs */
151 /* GCR_REV - Indicates the Coherence Manager revision */
165 /* GCR_ERR_CONTROL - Control error checking logic */
167 #define CM_GCR_ERR_CONTROL_L2_ECC_EN BIT(1)
168 #define CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT BIT(0)
170 /* GCR_ERR_MASK - Control which errors are reported as interrupts */
171 GCR_ACCESSOR_RW(64, 0x040, error_mask)
173 /* GCR_ERR_CAUSE - Indicates the type of error that occurred */
174 GCR_ACCESSOR_RW(64, 0x048, error_cause)
179 /* GCR_ERR_ADDR - Indicates the address associated with an error */
180 GCR_ACCESSOR_RW(64, 0x050, error_addr)
182 /* GCR_ERR_MULT - Indicates when multiple errors have occurred */
183 GCR_ACCESSOR_RW(64, 0x058, error_mult)
186 /* GCR_L2_ONLY_SYNC_BASE - Base address of the L2 cache-only sync region */
187 GCR_ACCESSOR_RW(64, 0x070, l2_only_sync_base)
189 #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN BIT(0)
191 /* GCR_GIC_BASE - Base address of the Global Interrupt Controller (GIC) */
192 GCR_ACCESSOR_RW(64, 0x080, gic_base)
194 #define CM_GCR_GIC_BASE_GICEN BIT(0)
196 /* GCR_CPC_BASE - Base address of the Cluster Power Controller (CPC) */
197 GCR_ACCESSOR_RW(64, 0x088, cpc_base)
199 #define CM_GCR_CPC_BASE_CPCEN BIT(0)
201 /* GCR_REGn_BASE - Base addresses of CM address regions */
202 GCR_ACCESSOR_RW(64, 0x090, reg0_base)
203 GCR_ACCESSOR_RW(64, 0x0a0, reg1_base)
204 GCR_ACCESSOR_RW(64, 0x0b0, reg2_base)
205 GCR_ACCESSOR_RW(64, 0x0c0, reg3_base)
208 /* GCR_REGn_MASK - Size & destination of CM address regions */
209 GCR_ACCESSOR_RW(64, 0x098, reg0_mask)
210 GCR_ACCESSOR_RW(64, 0x0a8, reg1_mask)
211 GCR_ACCESSOR_RW(64, 0x0b8, reg2_mask)
212 GCR_ACCESSOR_RW(64, 0x0c8, reg3_mask)
215 #define CM_GCR_REGn_MASK_CCAOVREN BIT(4)
216 #define CM_GCR_REGn_MASK_DROPL2 BIT(2)
223 /* GCR_GIC_STATUS - Indicates presence of a Global Interrupt Controller (GIC) */
225 #define CM_GCR_GIC_STATUS_EX BIT(0)
227 /* GCR_CPC_STATUS - Indicates presence of a Cluster Power Controller (CPC) */
229 #define CM_GCR_CPC_STATUS_EX BIT(0)
231 /* GCR_L2_CONFIG - Indicates L2 cache configuration when Config5.L2C=1 */
233 #define CM_GCR_L2_CONFIG_BYPASS BIT(20)
238 /* GCR_SYS_CONFIG2 - Further information about the system */
242 /* GCR_L2_PFT_CONTROL - Controls hardware L2 prefetching */
245 #define CM_GCR_L2_PFT_CONTROL_PFTEN BIT(8)
248 /* GCR_L2_PFT_CONTROL_B - Controls hardware L2 prefetching */
250 #define CM_GCR_L2_PFT_CONTROL_B_CEN BIT(8)
253 /* GCR_L2SM_COP - L2 cache op state machine control */
255 #define CM_GCR_L2SM_COP_PRESENT BIT(31)
262 #define CM_GCR_L2SM_COP_RUNNING BIT(5)
275 /* GCR_L2SM_TAG_ADDR_COP - L2 cache op state machine address control */
276 GCR_ACCESSOR_RW(64, 0x628, l2sm_tag_addr_cop)
280 /* GCR_BEV_BASE - Controls the location of the BEV for powered up cores */
281 GCR_ACCESSOR_RW(64, 0x680, bev_base)
283 /* GCR_Cx_RESET_RELEASE - Controls core reset for CM 1.x */
286 /* GCR_Cx_COHERENCE - Controls core coherence */
289 #define CM3_GCR_Cx_COHERENCE_COHEN BIT(0)
291 /* GCR_Cx_CONFIG - Information about a core's configuration */
296 /* GCR_Cx_OTHER - Configure the core-other/redirect GCR block */
299 #define CM_GCR_Cx_OTHER_CLUSTER_EN BIT(31) /* CM >= 3.5 */
300 #define CM_GCR_Cx_OTHER_GIC_EN BIT(30) /* CM >= 3.5 */
311 /* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */
315 /* GCR_Cx_ID - Identify the current core */
320 /* GCR_Cx_RESET_EXT_BASE - Configure behaviour when cores reset or power up */
322 #define CM_GCR_Cx_RESET_EXT_BASE_EVARESET BIT(31)
323 #define CM_GCR_Cx_RESET_EXT_BASE_UEB BIT(30)
326 #define CM_GCR_Cx_RESET_EXT_BASE_PRESENT BIT(0)
329 * mips_cm_l2sync - perform an L2-only sync operation
331 * If an L2-only sync region is present in the system then this function
332 * performs and L2-only sync and returns zero. Otherwise it returns -ENODEV.
337 return -ENODEV; in mips_cm_l2sync()
344 * mips_cm_revision() - return CM revision
358 * mips_cm_max_vp_width() - return the width in bits of VP indices
387 * mips_cm_vp_id() - calculate the hardware VP ID for a CPU
407 * mips_cm_lock_other - lock access to redirect/other region
420 * mips_cm_unlock_other() calls cannot be pre-empted by anything which may
428 * mips_cm_unlock_other - unlock access to redirect/other region
444 * mips_cm_lock_other_cpu - lock access to redirect/other region