Lines Matching full:has
360 #define MIPS_CPU_TLB BIT_ULL( 0) /* CPU has TLB */
364 #define MIPS_CPU_FPU BIT_ULL( 5) /* CPU has FPU */
375 #define MIPS_CPU_LLSC BIT_ULL(16) /* CPU has ll/sc instructions */
377 #define MIPS_CPU_PREFETCH BIT_ULL(18) /* CPU has usable prefetch */
380 #define MIPS_CPU_ULRI BIT_ULL(21) /* CPU has ULRI feature */
381 #define MIPS_CPU_PCI BIT_ULL(22) /* CPU has Perf Ctr Int indicator */
382 #define MIPS_CPU_RIXI BIT_ULL(23) /* CPU has TLB Read/eXec Inhibit */
383 #define MIPS_CPU_MICROMIPS BIT_ULL(24) /* CPU has microMIPS capability */
388 #define MIPS_CPU_RIXIEX BIT_ULL(29) /* CPU has unique exception codes for {Read, Execute}-Inhibit …
393 #define MIPS_CPU_CDMM BIT_ULL(34) /* CPU has Common Device Memory Map */
395 #define MIPS_CPU_FTLB BIT_ULL(37) /* CPU has Fixed-page-size TLB */
399 #define MIPS_CPU_LDPTE BIT_ULL(41) /* CPU has ldpte/lddir instructions */
401 #define MIPS_CPU_EBASE_WG BIT_ULL(43) /* CPU has EBase.WG */
402 #define MIPS_CPU_BADINSTR BIT_ULL(44) /* CPU has BadInstr register */
403 #define MIPS_CPU_BADINSTRP BIT_ULL(45) /* CPU has BadInstrP register */
404 #define MIPS_CPU_CTXTC BIT_ULL(46) /* CPU has [X]ConfigContext registers */
405 #define MIPS_CPU_PERF BIT_ULL(47) /* CPU has MIPS performance counters */
406 #define MIPS_CPU_GUESTCTL0EXT BIT_ULL(48) /* CPU has VZ GuestCtl0Ext register */
407 #define MIPS_CPU_GUESTCTL1 BIT_ULL(49) /* CPU has VZ GuestCtl1 register */
408 #define MIPS_CPU_GUESTCTL2 BIT_ULL(50) /* CPU has VZ GuestCtl2 register */
410 #define MIPS_CPU_DRG BIT_ULL(52) /* CPU has VZ Direct Root to Guest (DRG) */
417 BIT_ULL(56) /* CPU has perf counters implemented per TC (MIPSMT ASE) */
422 #define MIPS_CPU_FTLBPAREX BIT_ULL(61) /* CPU has FTLB parity exception */
423 #define MIPS_CPU_GSEXCEX BIT_ULL(62) /* CPU has GSExc exception */