Lines Matching +full:mtk +full:- +full:xhci
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 #include <dt-bindings/interrupt-controller/mips-gic.h>
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/clock/mt7621-clk.h>
5 #include <dt-bindings/reset/mt7621-reset.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
10 compatible = "mediatek,mt7621-soc";
13 #address-cells = <1>;
14 #size-cells = <0>;
30 #address-cells = <0>;
31 #interrupt-cells = <1>;
32 interrupt-controller;
33 compatible = "mti,cpu-interrupt-controller";
36 mmc_fixed_3v3: regulator-3v3 {
37 compatible = "regulator-fixed";
38 regulator-name = "mmc_power";
39 regulator-min-microvolt = <3300000>;
40 regulator-max-microvolt = <3300000>;
41 enable-active-high;
42 regulator-always-on;
45 mmc_fixed_1v8_io: regulator-1v8 {
46 compatible = "regulator-fixed";
47 regulator-name = "mmc_io";
48 regulator-min-microvolt = <1800000>;
49 regulator-max-microvolt = <1800000>;
50 enable-active-high;
51 regulator-always-on;
59 #address-cells = <1>;
60 #size-cells = <1>;
63 compatible = "mediatek,mt7621-sysc", "syscon";
65 #clock-cells = <1>;
66 #reset-cells = <1>;
68 clock-output-names = "xtal", "cpu", "bus",
74 compatible = "mediatek,mt7621-wdt";
79 #gpio-cells = <2>;
80 #interrupt-cells = <2>;
81 compatible = "mediatek,mt7621-gpio";
82 gpio-controller;
83 gpio-ranges = <&pinctrl 0 0 95>;
84 interrupt-controller;
86 interrupt-parent = <&gic>;
91 compatible = "mediatek,mt7621-i2c";
95 clock-names = "i2c";
97 reset-names = "i2c";
99 #address-cells = <1>;
100 #size-cells = <0>;
104 pinctrl-names = "default";
105 pinctrl-0 = <&i2c_pins>;
108 memc: memory-controller@5000 {
109 compatible = "mediatek,mt7621-memc", "syscon";
119 interrupt-parent = <&gic>;
122 reg-shift = <2>;
123 reg-io-width = <4>;
124 no-loopback-test;
130 compatible = "ralink,mt7621-spi";
134 clock-names = "spi";
137 reset-names = "spi";
139 #address-cells = <1>;
140 #size-cells = <0>;
142 pinctrl-names = "default";
143 pinctrl-0 = <&spi_pins>;
148 compatible = "ralink,mt7621-pinctrl";
150 i2c_pins: i2c0-pins {
157 spi_pins: spi0-pins {
164 uart1_pins: uart1-pins {
171 uart2_pins: uart2-pins {
178 uart3_pins: uart3-pins {
185 rgmii1_pins: rgmii1-pins {
192 rgmii2_pins: rgmii2-pins {
199 mdio_pins: mdio0-pins {
206 pcie_pins: pcie0-pins {
213 nand_pins: nand0-pins {
214 spi-pinmux {
219 sdhci-pinmux {
225 sdhci_pins: sdhci0-pins {
236 compatible = "mediatek,mt7620-mmc";
239 bus-width = <4>;
240 max-frequency = <48000000>;
241 cap-sd-highspeed;
242 cap-mmc-highspeed;
243 vmmc-supply = <&mmc_fixed_3v3>;
244 vqmmc-supply = <&mmc_fixed_1v8_io>;
245 disable-wp;
247 pinctrl-names = "default", "state_uhs";
248 pinctrl-0 = <&sdhci_pins>;
249 pinctrl-1 = <&sdhci_pins>;
253 clock-names = "source", "hclk";
255 interrupt-parent = <&gic>;
260 compatible = "mediatek,mt8173-xhci", "mediatek,mtk-xhci";
263 reg-names = "mac", "ippc";
266 clock-names = "sys_ck";
268 interrupt-parent = <&gic>;
272 gic: interrupt-controller@1fbc0000 {
276 interrupt-controller;
277 #interrupt-cells = <3>;
279 mti,reserved-cpu-vectors = <7>;
282 compatible = "mti,gic-timer";
289 compatible = "mti,mips-cpc";
294 compatible = "mti,mips-cdmm";
299 compatible = "mediatek,mt7621-eth";
304 clock-names = "fe", "ethif";
306 #address-cells = <1>;
307 #size-cells = <0>;
310 reset-names = "fe", "eth";
312 interrupt-parent = <&gic>;
317 pinctrl-names = "default";
318 pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>;
321 compatible = "mediatek,eth-mac";
323 phy-mode = "trgmii";
325 fixed-link {
327 full-duplex;
333 compatible = "mediatek,eth-mac";
336 phy-mode = "rgmii";
339 mdio: mdio-bus {
340 #address-cells = <1>;
341 #size-cells = <0>;
348 reset-names = "mcm";
349 interrupt-controller;
350 #interrupt-cells = <1>;
354 #address-cells = <1>;
355 #size-cells = <0>;
391 phy-mode = "trgmii";
393 fixed-link {
395 full-duplex;
405 compatible = "mediatek,mt7621-pci";
406 reg = <0x1e140000 0x100>, /* host-pci bridge registers */
410 #address-cells = <3>;
411 #size-cells = <2>;
413 pinctrl-names = "default";
414 pinctrl-0 = <&pcie_pins>;
421 #interrupt-cells = <1>;
422 interrupt-map-mask = <0xF800 0 0 0>;
423 interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
429 reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
433 #address-cells = <3>;
434 #size-cells = <2>;
436 #interrupt-cells = <1>;
437 interrupt-map-mask = <0 0 0 0>;
438 interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
442 phy-names = "pcie-phy0";
448 #address-cells = <3>;
449 #size-cells = <2>;
451 #interrupt-cells = <1>;
452 interrupt-map-mask = <0 0 0 0>;
453 interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
457 phy-names = "pcie-phy1";
463 #address-cells = <3>;
464 #size-cells = <2>;
466 #interrupt-cells = <1>;
467 interrupt-map-mask = <0 0 0 0>;
468 interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
472 phy-names = "pcie-phy2";
477 pcie0_phy: pcie-phy@1e149000 {
478 compatible = "mediatek,mt7621-pci-phy";
481 #phy-cells = <1>;
484 pcie2_phy: pcie-phy@1e14a000 {
485 compatible = "mediatek,mt7621-pci-phy";
488 #phy-cells = <1>;