Lines Matching +full:0 +full:x1e140000

14 		#size-cells = <0>;
16 		cpu@0 {
19 			reg = <0>;
30 		#address-cells = <0>;
56 		reg = <0x1e000000 0x100000>;
57 		ranges = <0x0 0x1e000000 0x0fffff>;
62 		sysc: syscon@0 {
64 			reg = <0x0 0x100>;
75 			reg = <0x100 0x100>;
83 			gpio-ranges = <&pinctrl 0 0 95>;
85 			reg = <0x600 0x100>;
92 			reg = <0x900 0x100>;
100 			#size-cells = <0>;
105 			pinctrl-0 = <&i2c_pins>;
110 			reg = <0x5000 0x1000>;
115 			reg = <0xc00 0x100>;
131 			reg = <0xb00 0x100>;
140 			#size-cells = <0>;
143 			pinctrl-0 = <&spi_pins>;
237 		reg = <0x1e130000 0x4000>;
248 		pinctrl-0 = <&sdhci_pins>;
261 		reg = <0x1e1c0000 0x1000
262 		       0x1e1d0700 0x0100>;
274 		reg = <0x1fbc0000 0x2000>;
290 		reg = <0x1fbf0000 0x8000>;
295 		reg = <0x1fbf8000 0x8000>;
300 		reg = <0x1e100000 0x10000>;
307 		#size-cells = <0>;
318 		pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>;
320 		gmac0: mac@0 {
322 			reg = <0>;
341 			#size-cells = <0>;
345 				reg = <0x1f>;
355 					#size-cells = <0>;
357 					port@0 {
359 						reg = <0>;
406 		reg = <0x1e140000 0x100>, /* host-pci bridge registers */
407 		      <0x1e142000 0x100>, /* pcie port 0 RC control registers */
408 		      <0x1e143000 0x100>, /* pcie port 1 RC control registers */
409 		      <0x1e144000 0x100>; /* pcie port 2 RC control registers */
414 		pinctrl-0 = <&pcie_pins>;
418 		ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
419 			 <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
422 		interrupt-map-mask = <0xF800 0 0 0>;
423 		interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
424 				<0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
425 				<0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
431 		pcie@0,0 {
432 			reg = <0x0000 0 0 0 0>;
437 			interrupt-map-mask = <0 0 0 0>;
438 			interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
446 		pcie@1,0 {
447 			reg = <0x0800 0 0 0 0>;
452 			interrupt-map-mask = <0 0 0 0>;
453 			interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
461 		pcie@2,0 {
462 			reg = <0x1000 0 0 0 0>;
467 			interrupt-map-mask = <0 0 0 0>;
468 			interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
471 			phys = <&pcie2_phy 0>;
479 		reg = <0x1e149000 0x0700>;
486 		reg = <0x1e14a000 0x0700>;