Lines Matching +full:0 +full:x50
34 #size-cells = <0>;
36 cpu@0 {
44 interrupts = <0 IRQ_TYPE_EDGE_RISING>;
49 #clock-cells = <0>;
57 #clock-cells = <0>;
65 reg = <0x1f801200 0x200>;
74 reg = <0x1f810000 0x1000>;
82 reg = <0x1f801400 0x400>;
89 reg = <0x1f860000 0x100>;
96 microchip,gpio-bank = <0>;
97 gpio-ranges = <&pic32_pinctrl 0 0 16>;
103 reg = <0x1f860100 0x100>;
111 gpio-ranges = <&pic32_pinctrl 0 16 16>;
117 reg = <0x1f860200 0x100>;
125 gpio-ranges = <&pic32_pinctrl 0 32 16>;
131 reg = <0x1f860300 0x100>;
139 gpio-ranges = <&pic32_pinctrl 0 48 16>;
145 reg = <0x1f860400 0x100>;
153 gpio-ranges = <&pic32_pinctrl 0 64 16>;
159 reg = <0x1f860500 0x100>;
167 gpio-ranges = <&pic32_pinctrl 0 80 16>;
173 reg = <0x1f860600 0x100>;
181 gpio-ranges = <&pic32_pinctrl 0 96 16>;
187 reg = <0x1f860700 0x100>;
195 gpio-ranges = <&pic32_pinctrl 0 112 16>;
203 reg = <0x1f860800 0x100>;
211 gpio-ranges = <&pic32_pinctrl 0 128 16>;
217 reg = <0x1f860900 0x100>;
225 gpio-ranges = <&pic32_pinctrl 0 144 16>;
230 reg = <0x1f8ec000 0x100>;
241 reg = <0x1f822000 0x50>;
251 reg = <0x1f822200 0x50>;
261 reg = <0x1f822400 0x50>;
271 reg = <0x1f822600 0x50>;
281 reg = <0x1f822800 0x50>;
291 reg = <0x1f822A00 0x50>;