Lines Matching +full:i2c +full:- +full:pins
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
11 compatible = "mscc,jr2-pcb111", "mscc,jr2";
22 i2c0_imux: i2c0-imux {
23 compatible = "i2c-mux-pinctrl";
24 #address-cells = <1>;
25 #size-cells = <0>;
26 i2c-parent = <&i2c0>;
27 pinctrl-names =
29 pinctrl-0 = <&i2cmux_0>;
30 pinctrl-1 = <&i2cmux_1>;
31 pinctrl-2 = <&i2cmux_2>;
32 pinctrl-3 = <&i2cmux_3>;
33 pinctrl-4 = <&i2cmux_pins_i>; // Added by convention for PoE
34 pinctrl-5 = <&i2cmux_pins_i>;
35 i2c149: i2c@0 {
37 #address-cells = <1>;
38 #size-cells = <0>;
40 i2c150: i2c@1 {
42 #address-cells = <1>;
43 #size-cells = <0>;
45 i2c151: i2c@2 {
47 #address-cells = <1>;
48 #size-cells = <0>;
50 i2c152: i2c@3 {
52 #address-cells = <1>;
53 #size-cells = <0>;
55 i2c203: i2c@4 {
57 #address-cells = <1>;
58 #size-cells = <0>;
64 synce_builtin_pins: synce-builtin-pins {
66 pins = "GPIO_49";
69 cpld_pins: cpld-pins {
71 pins = "GPIO_50";
74 cpld_fifo_pins: synce-builtin-pins {
76 pins = "GPIO_51";
82 i2cmux_pins_i: i2cmux-pins {
83 pins = "GPIO_17", "GPIO_18";
85 output-low;
87 i2cmux_0: i2cmux-0-pins {
88 pins = "GPIO_17";
90 output-high;
92 i2cmux_1: i2cmux-1-pins {
93 pins = "GPIO_18";
95 output-high;
97 i2cmux_2: i2cmux-2-pins {
98 pins = "GPIO_20";
100 output-high;
102 i2cmux_3: i2cmux-3-pins {
103 pins = "GPIO_21";
105 output-high;