Lines Matching +full:0 +full:x16000000
13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
18 reg = <0>;
26 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
35 #address-cells = <0>;
43 reg = <0x10001000 0x50>;
54 #clock-cells = <0>;
59 #clock-cells = <0>;
65 reg = <0x10000000 0x100>;
68 ranges = <0x0 0x10000000 0x100>;
77 reg = <0x3c 0x10>;
81 #phy-cells = <0>;
88 reg = <0xd8 0x8>;
98 reg = <0x10002000 0x1000>;
101 ranges = <0x0 0x10002000 0x1000>;
116 watchdog: watchdog@0 {
118 reg = <0x0 0xc>;
126 reg = <0x40 0x80>;
140 reg = <0xe0 0x20>;
151 reg = <0x10003000 0x4c>;
162 reg = <0x10010000 0x600>;
165 #size-cells = <0>;
167 gpa: gpio@0 {
169 reg = <0>;
172 gpio-ranges = <&pinctrl 0 0 32>;
187 gpio-ranges = <&pinctrl 0 32 32>;
202 gpio-ranges = <&pinctrl 0 64 32>;
217 gpio-ranges = <&pinctrl 0 96 32>;
232 gpio-ranges = <&pinctrl 0 128 32>;
247 gpio-ranges = <&pinctrl 0 160 32>;
260 reg = <0x10043000 0x1c>;
262 #size-cells = <0>;
270 dmas = <&dma JZ4780_DMA_SSI0_RX 0xffffffff>,
271 <&dma JZ4780_DMA_SSI0_TX 0xffffffff>;
279 reg = <0x10030000 0x100>;
292 reg = <0x10031000 0x100>;
305 reg = <0x10032000 0x100>;
318 reg = <0x10033000 0x100>;
331 reg = <0x10034000 0x100>;
344 reg = <0x10044000 0x1c>;
346 #size-sells = <0>;
354 dmas = <&dma JZ4780_DMA_SSI1_RX 0xffffffff>,
355 <&dma JZ4780_DMA_SSI1_TX 0xffffffff>;
364 #size-cells = <0>;
366 reg = <0x10050000 0x1000>;
374 pinctrl-0 = <&pins_i2c0_data>;
382 #size-cells = <0>;
383 reg = <0x10051000 0x1000>;
391 pinctrl-0 = <&pins_i2c1_data>;
399 #size-cells = <0>;
400 reg = <0x10052000 0x1000>;
408 pinctrl-0 = <&pins_i2c2_data>;
416 #size-cells = <0>;
417 reg = <0x10053000 0x1000>;
425 pinctrl-0 = <&pins_i2c3_data>;
433 #size-cells = <0>;
434 reg = <0x10054000 0x1000>;
442 pinctrl-0 = <&pins_i2c4_data>;
449 reg = <0x10180000 0x8000>;
463 reg = <0x13050000 0x1800>;
476 reg = <0x130a0000 0x1800>;
489 reg = <0x13410000 0x10000>;
492 ranges = <0 0 0x13410000 0x10000>,
493 <1 0 0x1b000000 0x1000000>,
494 <2 0 0x1a000000 0x1000000>,
495 <3 0 0x19000000 0x1000000>,
496 <4 0 0x18000000 0x1000000>,
497 <5 0 0x17000000 0x1000000>,
498 <6 0 0x16000000 0x1000000>;
505 reg = <0 0xd0 0x30>;
514 reg = <0x22 0x6>;
521 reg = <0x13420000 0x400>, <0x13421000 0x40>;
532 reg = <0x13450000 0x1000>;
543 dmas = <&dma JZ4780_DMA_MSC0_RX 0xffffffff>,
544 <&dma JZ4780_DMA_MSC0_TX 0xffffffff>;
552 reg = <0x13460000 0x1000>;
563 dmas = <&dma JZ4780_DMA_MSC1_RX 0xffffffff>,
564 <&dma JZ4780_DMA_MSC1_TX 0xffffffff>;
572 reg = <0x134d0000 0x10000>;
581 reg = <0x13500000 0x40000>;