Lines Matching +full:0 +full:x4c00000
27 reg = <0x0 0x10000000
28 0x30000000 0x30000000>;
65 gpios = <&gpc 0 GPIO_ACTIVE_HIGH>;
70 eth0_power: fixedregulator@0 {
133 assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>,
136 assigned-clock-rates = <48000000>, <0>, <54000000>, <0>, <27000000>;
142 * use channel #0 and #1 for the per cpu system timers,
160 pinctrl-0 = <&pins_mmc0>;
173 pinctrl-0 = <&pins_mmc1>;
188 pinctrl-0 = <&pins_uart0>;
195 pinctrl-0 = <&pins_uart1>;
202 pinctrl-0 = <&pins_uart2>;
219 pinctrl-0 = <&pins_uart3>;
226 pinctrl-0 = <&pins_uart4>;
233 pinctrl-0 = <&pins_i2c0>;
239 reg = <0x5a>;
319 pinctrl-0 = <&pins_i2c1>;
327 pinctrl-0 = <&pins_i2c2>;
335 pinctrl-0 = <&pins_i2c3>;
343 pinctrl-0 = <&pins_i2c4>;
349 reg = <0x51>;
361 reg = <1 0 0x1000000>;
364 #size-cells = <0>;
379 pinctrl-0 = <&pins_nemc>;
390 pinctrl-0 = <&pins_nemc_cs1>;
397 partition@0 {
399 reg = <0x0 0x0 0x0 0x800000>;
404 reg = <0x0 0x800000 0x0 0x200000>;
409 reg = <0x0 0xa00000 0x0 0x200000>;
414 reg = <0x0 0xc00000 0x0 0x4000000>;
419 reg = <0x0 0x4c00000 0x1 0xfb400000>;
430 pinctrl-0 = <&pins_nemc_cs6>;
432 reg = <6 0 1 /* addr */
568 pinctrl-0 = <&pins_hdmi_ddc>;
572 #size-cells = <0>;
574 port@0 {
575 reg = <0>;