1 // SPDX-License-Identifier: GPL-2.0-or-later
18 #include <linux/clk-provider.h>
21 #include <asm/mach-ar7/ar7.h>
46 	u32 ctrl;  member
65 	struct tnetd7300_clock dsp;  member
69 	u32 ctrl;  member
85 	struct tnetd7200_clock dsp;  member
107 				freq = abs(base / j * i / k - target);  in approximate()
166 	u32 ctrl = readl(&clock->ctrl);  in tnetd7300_get_clock()  local
167 	u32 pll = readl(&clock->pll);  in tnetd7300_get_clock()
168 	int prediv = ((ctrl & PREDIV_MASK) >> PREDIV_SHIFT) + 1;  in tnetd7300_get_clock()
169 	int postdiv = (ctrl & POSTDIV_MASK) + 1;  in tnetd7300_get_clock()
197 			(base_clock * (mul - 1)) >> 2;  in tnetd7300_get_clock()
230 	writel(((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1), &clock->ctrl);  in tnetd7300_set_clock()
232 	writel(4, &clock->pll);  in tnetd7300_set_clock()
233 	while (readl(&clock->pll) & PLL_STATUS)  in tnetd7300_set_clock()
235 	writel(((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e, &clock->pll);  in tnetd7300_set_clock()
249 		&clocks->bus, bootcr, AR7_AFE_CLOCK);  in tnetd7300_init_clocks()
253 			&clocks->cpu, bootcr, AR7_AFE_CLOCK);  in tnetd7300_init_clocks()
259 		tnetd7300_set_clock(DSP_PLL_SOURCE_SHIFT, &clocks->dsp,  in tnetd7300_init_clocks()
267 	clk = clk_register_fixed_rate(NULL, "dsp", NULL, 0, dsp_clk);  in tnetd7300_init_clocks()
268 	clkdev_create(clk, "dsp", NULL);  in tnetd7300_init_clocks()
279 	writel(0, &clock->ctrl);  in tnetd7200_set_clock()
280 	writel(DIVISOR_ENABLE_MASK | ((prediv - 1) & 0x1F), &clock->prediv);  in tnetd7200_set_clock()
281 	writel((mul - 1) & 0xF, &clock->mul);  in tnetd7200_set_clock()
283 	while (readl(&clock->status) & 0x1)  in tnetd7200_set_clock()
286 	writel(DIVISOR_ENABLE_MASK | ((postdiv - 1) & 0x1F), &clock->postdiv);  in tnetd7200_set_clock()
288 	writel(readl(&clock->cmden) | 1, &clock->cmden);  in tnetd7200_set_clock()
289 	writel(readl(&clock->cmd) | 1, &clock->cmd);  in tnetd7200_set_clock()
291 	while (readl(&clock->status) & 0x1)  in tnetd7200_set_clock()
294 	writel(DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F), &clock->postdiv2);  in tnetd7200_set_clock()
296 	writel(readl(&clock->cmden) | 1, &clock->cmden);  in tnetd7200_set_clock()
297 	writel(readl(&clock->cmd) | 1, &clock->cmd);  in tnetd7200_set_clock()
299 	while (readl(&clock->status) & 0x1)  in tnetd7200_set_clock()
302 	writel(readl(&clock->ctrl) | 1, &clock->ctrl);  in tnetd7200_set_clock()
348 		printk(KERN_INFO "Clocks: Setting DSP clock\n");  in tnetd7200_init_clocks()
353 		tnetd7200_set_clock(dsp_base, &clocks->dsp,  in tnetd7200_init_clocks()
362 		tnetd7200_set_clock(cpu_base, &clocks->cpu,  in tnetd7200_init_clocks()
363 			cpu_prediv, cpu_postdiv, -1, cpu_mul,  in tnetd7200_init_clocks()
375 			tnetd7200_set_clock(cpu_base, &clocks->cpu,  in tnetd7200_init_clocks()
376 				cpu_prediv, cpu_postdiv, -1, cpu_mul,  in tnetd7200_init_clocks()
379 			printk(KERN_INFO "Clocks: Setting DSP clock\n");  in tnetd7200_init_clocks()
383 			tnetd7200_set_clock(dsp_base, &clocks->dsp,  in tnetd7200_init_clocks()
389 			printk(KERN_INFO "Clocks: Setting DSP clock\n");  in tnetd7200_init_clocks()
394 			tnetd7200_set_clock(dsp_base, &clocks->dsp,  in tnetd7200_init_clocks()
405 	tnetd7200_set_clock(usb_base, &clocks->usb,  in tnetd7200_init_clocks()
406 		usb_prediv, usb_postdiv, -1, usb_mul,  in tnetd7200_init_clocks()
414 	clkdev_create(clk, "dsp", NULL);  in tnetd7200_init_clocks()