Lines Matching +full:bus +full:- +full:range
1 // SPDX-License-Identifier: GPL-2.0-or-later
12 * Common pmac/prep/chrp pci routines. -- Cort
35 #include <asm/pci-bridge.h>
60 phb->global_number = global_phb_number++; in pcibios_alloc_controller()
61 list_add_tail(&phb->list_node, &hose_list); in pcibios_alloc_controller()
63 phb->dn = dev; in pcibios_alloc_controller()
64 phb->is_dynamic = mem_init_done; in pcibios_alloc_controller()
71 list_del(&phb->list_node); in pcibios_free_controller()
74 if (phb->is_dynamic) in pcibios_free_controller()
80 return resource_size(&hose->io_resource); in pcibios_io_size()
92 if (address >= hose->io_base_virt && in pcibios_vaddr_is_ioport()
93 address < (hose->io_base_virt + size)) { in pcibios_vaddr_is_ioport()
111 if (address >= hose->io_base_phys && in pci_address_to_pio()
112 address < (hose->io_base_phys + size)) { in pci_address_to_pio()
114 (unsigned long)hose->io_base_virt - _IO_BASE; in pci_address_to_pio()
115 ret = base + (address - hose->io_base_phys); in pci_address_to_pio()
126 * PCI bus numbers have not yet been assigned, and you need to
137 if (hose->dn == node) in pci_find_hose_for_OF_device()
139 node = node->parent; in pci_find_hose_for_OF_device()
146 /* No special bus mastering setup handling */ in pcibios_set_master()
150 * Platform support for /proc/bus/pci/X/Y mmap()s.
155 struct pci_controller *hose = pci_bus_to_host(pdev->bus); in pci_iobar_pfn()
159 return -EINVAL; /* should never happen */ in pci_iobar_pfn()
162 ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE; in pci_iobar_pfn()
164 vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT; in pci_iobar_pfn()
168 /* This provides legacy IO read access on a bus */
169 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) in pci_legacy_read() argument
172 struct pci_controller *hose = pci_bus_to_host(bus); in pci_legacy_read()
173 struct resource *rp = &hose->io_resource; in pci_legacy_read()
176 /* Check if port can be supported by that bus. We only check in pci_legacy_read()
177 * the ranges of the PHB though, not the bus itself as the rules in pci_legacy_read()
181 offset = (unsigned long)hose->io_base_virt - _IO_BASE; in pci_legacy_read()
184 if (!(rp->flags & IORESOURCE_IO)) in pci_legacy_read()
185 return -ENXIO; in pci_legacy_read()
186 if (offset < rp->start || (offset + size) > rp->end) in pci_legacy_read()
187 return -ENXIO; in pci_legacy_read()
188 addr = hose->io_base_virt + port; in pci_legacy_read()
196 return -EINVAL; in pci_legacy_read()
201 return -EINVAL; in pci_legacy_read()
205 return -EINVAL; in pci_legacy_read()
208 /* This provides legacy IO write access on a bus */
209 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) in pci_legacy_write() argument
212 struct pci_controller *hose = pci_bus_to_host(bus); in pci_legacy_write()
213 struct resource *rp = &hose->io_resource; in pci_legacy_write()
216 /* Check if port can be supported by that bus. We only check in pci_legacy_write()
217 * the ranges of the PHB though, not the bus itself as the rules in pci_legacy_write()
221 offset = (unsigned long)hose->io_base_virt - _IO_BASE; in pci_legacy_write()
224 if (!(rp->flags & IORESOURCE_IO)) in pci_legacy_write()
225 return -ENXIO; in pci_legacy_write()
226 if (offset < rp->start || (offset + size) > rp->end) in pci_legacy_write()
227 return -ENXIO; in pci_legacy_write()
228 addr = hose->io_base_virt + port; in pci_legacy_write()
241 return -EINVAL; in pci_legacy_write()
246 return -EINVAL; in pci_legacy_write()
250 return -EINVAL; in pci_legacy_write()
253 /* This provides legacy IO or memory mmap access on a bus */
254 int pci_mmap_legacy_page_range(struct pci_bus *bus, in pci_mmap_legacy_page_range() argument
258 struct pci_controller *hose = pci_bus_to_host(bus); in pci_mmap_legacy_page_range()
260 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; in pci_mmap_legacy_page_range()
261 resource_size_t size = vma->vm_end - vma->vm_start; in pci_mmap_legacy_page_range()
265 pci_domain_nr(bus), bus->number, in pci_mmap_legacy_page_range()
268 (unsigned long long)(offset + size - 1)); in pci_mmap_legacy_page_range()
278 if ((offset + size) > hose->isa_mem_size) { in pci_mmap_legacy_page_range()
279 pr_debug("Process %s (pid:%d) mapped non-existing PCI", in pci_mmap_legacy_page_range()
280 current->comm, current->pid); in pci_mmap_legacy_page_range()
282 pci_domain_nr(bus), bus->number); in pci_mmap_legacy_page_range()
283 if (vma->vm_flags & VM_SHARED) in pci_mmap_legacy_page_range()
287 offset += hose->isa_mem_phys; in pci_mmap_legacy_page_range()
289 unsigned long io_offset = (unsigned long)hose->io_base_virt - in pci_mmap_legacy_page_range()
292 rp = &hose->io_resource; in pci_mmap_legacy_page_range()
293 if (!(rp->flags & IORESOURCE_IO)) in pci_mmap_legacy_page_range()
294 return -ENXIO; in pci_mmap_legacy_page_range()
295 if (roffset < rp->start || (roffset + size) > rp->end) in pci_mmap_legacy_page_range()
296 return -ENXIO; in pci_mmap_legacy_page_range()
297 offset += hose->io_base_phys; in pci_mmap_legacy_page_range()
299 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); in pci_mmap_legacy_page_range()
301 vma->vm_pgoff = offset >> PAGE_SHIFT; in pci_mmap_legacy_page_range()
302 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); in pci_mmap_legacy_page_range()
303 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, in pci_mmap_legacy_page_range()
304 vma->vm_end - vma->vm_start, in pci_mmap_legacy_page_range()
305 vma->vm_page_prot); in pci_mmap_legacy_page_range()
314 if (rsrc->flags & IORESOURCE_IO) { in pci_resource_to_user()
315 pcibios_resource_to_bus(dev->bus, ®ion, in pci_resource_to_user()
326 * That means we may have 64-bit values where some apps only expect in pci_resource_to_user()
327 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO). in pci_resource_to_user()
329 *start = rsrc->start; in pci_resource_to_user()
330 *end = rsrc->end; in pci_resource_to_user()
334 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
337 * @primary: set if primary bus (32 bits only, soon to be deprecated)
346 * - We can only cope with one IO space range and up to 3 Memory space
350 * - We can only cope with all memory ranges having the same offset
359 * - Some busses have IO space not starting at 0, which causes trouble with
363 * - Some 32 bits platforms such as 4xx can have physical space larger than
369 int memno = 0, isa_hole = -1; in pci_process_bridge_OF_ranges()
372 struct of_pci_range range; in pci_process_bridge_OF_ranges() local
383 for_each_of_pci_range(&parser, &range) { in pci_process_bridge_OF_ranges()
386 /* If we failed translation or got a zero-sized region in pci_process_bridge_OF_ranges()
391 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0) in pci_process_bridge_OF_ranges()
396 switch (range.flags & IORESOURCE_TYPE_BITS) { in pci_process_bridge_OF_ranges()
398 pr_info(" IO 0x%016llx..0x%016llx -> 0x%016llx\n", in pci_process_bridge_OF_ranges()
399 range.cpu_addr, range.cpu_addr + range.size - 1, in pci_process_bridge_OF_ranges()
400 range.pci_addr); in pci_process_bridge_OF_ranges()
402 /* We support only one IO range */ in pci_process_bridge_OF_ranges()
403 if (hose->pci_io_size) { in pci_process_bridge_OF_ranges()
404 pr_info(" \\--> Skipped (too many) !\n"); in pci_process_bridge_OF_ranges()
408 if (range.size > 0x01000000) in pci_process_bridge_OF_ranges()
409 range.size = 0x01000000; in pci_process_bridge_OF_ranges()
412 hose->io_base_virt = ioremap(range.cpu_addr, in pci_process_bridge_OF_ranges()
413 range.size); in pci_process_bridge_OF_ranges()
418 (unsigned long)hose->io_base_virt; in pci_process_bridge_OF_ranges()
422 hose->pci_io_size = range.pci_addr + range.size; in pci_process_bridge_OF_ranges()
423 hose->io_base_phys = range.cpu_addr - range.pci_addr; in pci_process_bridge_OF_ranges()
426 res = &hose->io_resource; in pci_process_bridge_OF_ranges()
427 range.cpu_addr = range.pci_addr; in pci_process_bridge_OF_ranges()
431 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", in pci_process_bridge_OF_ranges()
432 range.cpu_addr, range.cpu_addr + range.size - 1, in pci_process_bridge_OF_ranges()
433 range.pci_addr, in pci_process_bridge_OF_ranges()
434 (range.flags & IORESOURCE_PREFETCH) ? in pci_process_bridge_OF_ranges()
439 pr_info(" \\--> Skipped (too many) !\n"); in pci_process_bridge_OF_ranges()
443 if (range.pci_addr == 0) { in pci_process_bridge_OF_ranges()
444 isa_mb = range.cpu_addr; in pci_process_bridge_OF_ranges()
447 isa_mem_base = range.cpu_addr; in pci_process_bridge_OF_ranges()
448 hose->isa_mem_phys = range.cpu_addr; in pci_process_bridge_OF_ranges()
449 hose->isa_mem_size = range.size; in pci_process_bridge_OF_ranges()
452 /* We get the PCI/Mem offset from the first range or in pci_process_bridge_OF_ranges()
457 (isa_hole >= 0 && range.pci_addr != 0 && in pci_process_bridge_OF_ranges()
458 hose->pci_mem_offset == isa_mb)) in pci_process_bridge_OF_ranges()
459 hose->pci_mem_offset = range.cpu_addr - in pci_process_bridge_OF_ranges()
460 range.pci_addr; in pci_process_bridge_OF_ranges()
461 else if (range.pci_addr != 0 && in pci_process_bridge_OF_ranges()
462 hose->pci_mem_offset != range.cpu_addr - in pci_process_bridge_OF_ranges()
463 range.pci_addr) { in pci_process_bridge_OF_ranges()
464 pr_info(" \\--> Skipped (offset mismatch) !\n"); in pci_process_bridge_OF_ranges()
469 res = &hose->mem_resources[memno++]; in pci_process_bridge_OF_ranges()
473 res->name = dev->full_name; in pci_process_bridge_OF_ranges()
474 res->flags = range.flags; in pci_process_bridge_OF_ranges()
475 res->start = range.cpu_addr; in pci_process_bridge_OF_ranges()
476 res->end = range.cpu_addr + range.size - 1; in pci_process_bridge_OF_ranges()
477 res->parent = res->child = res->sibling = NULL; in pci_process_bridge_OF_ranges()
481 /* If there's an ISA hole and the pci_mem_offset is -not- matching in pci_process_bridge_OF_ranges()
485 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) { in pci_process_bridge_OF_ranges()
489 memmove(&hose->mem_resources[isa_hole], in pci_process_bridge_OF_ranges()
490 &hose->mem_resources[next], in pci_process_bridge_OF_ranges()
491 sizeof(struct resource) * (memno - next)); in pci_process_bridge_OF_ranges()
492 hose->mem_resources[--memno].flags = 0; in pci_process_bridge_OF_ranges()
497 int pci_proc_domain(struct pci_bus *bus) in pci_proc_domain() argument
499 return pci_domain_nr(bus); in pci_proc_domain()
507 struct pci_controller *hose = pci_bus_to_host(dev->bus); in pcibios_fixup_resources()
516 struct resource *res = dev->resource + i; in pcibios_fixup_resources()
517 if (!res->flags) in pcibios_fixup_resources()
519 if (res->start == 0) { in pcibios_fixup_resources()
520 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]", in pcibios_fixup_resources()
522 (unsigned long long)res->start, in pcibios_fixup_resources()
523 (unsigned long long)res->end, in pcibios_fixup_resources()
524 (unsigned int)res->flags); in pcibios_fixup_resources()
526 res->end -= res->start; in pcibios_fixup_resources()
527 res->start = 0; in pcibios_fixup_resources()
528 res->flags |= IORESOURCE_UNSET; in pcibios_fixup_resources()
532 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n", in pcibios_fixup_resources()
534 (unsigned long long)res->start, in pcibios_fixup_resources()
535 (unsigned long long)res->end, in pcibios_fixup_resources()
536 (unsigned int)res->flags); in pcibios_fixup_resources()
543 dev->irq = of_irq_parse_and_map_pci(dev, 0, 0); in pcibios_device_add()
558 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { in reparent_resources()
559 if (p->end < res->start) in reparent_resources()
561 if (res->end < p->start) in reparent_resources()
563 if (p->start < res->start || p->end > res->end) in reparent_resources()
564 return -1; /* not completely contained */ in reparent_resources()
569 return -1; /* didn't find any conflicting entries? */ in reparent_resources()
570 res->parent = parent; in reparent_resources()
571 res->child = *firstpp; in reparent_resources()
572 res->sibling = *pp; in reparent_resources()
575 for (p = res->child; p != NULL; p = p->sibling) { in reparent_resources()
576 p->parent = res; in reparent_resources()
578 p->name, in reparent_resources()
579 (unsigned long long)p->start, in reparent_resources()
580 (unsigned long long)p->end, res->name); in reparent_resources()
588 * On the other hand, we cannot just re-allocate all devices, as it would
594 * - I/O or memory regions not configured
595 * - regions configured, but not enabled in the command register
596 * - bogus I/O addresses above 64K used
597 * - expansion ROMs left enabled (this may sound harmless, but given
603 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
618 static void pcibios_allocate_bus_resources(struct pci_bus *bus) in pcibios_allocate_bus_resources() argument
624 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", in pcibios_allocate_bus_resources()
625 pci_domain_nr(bus), bus->number); in pcibios_allocate_bus_resources()
627 pci_bus_for_each_resource(bus, res, i) { in pcibios_allocate_bus_resources()
628 if (!res || !res->flags in pcibios_allocate_bus_resources()
629 || res->start > res->end || res->parent) in pcibios_allocate_bus_resources()
631 if (bus->parent == NULL) in pcibios_allocate_bus_resources()
632 pr = (res->flags & IORESOURCE_IO) ? in pcibios_allocate_bus_resources()
635 /* Don't bother with non-root busses when in pcibios_allocate_bus_resources()
636 * re-assigning all resources. We clear the in pcibios_allocate_bus_resources()
638 * and as such ensure proper re-allocation in pcibios_allocate_bus_resources()
641 pr = pci_find_parent_resource(bus->self, res); in pcibios_allocate_bus_resources()
645 * bridge is transparent -- paulus in pcibios_allocate_bus_resources()
651 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx ", in pcibios_allocate_bus_resources()
652 bus->self ? pci_name(bus->self) : "PHB", in pcibios_allocate_bus_resources()
653 bus->number, i, in pcibios_allocate_bus_resources()
654 (unsigned long long)res->start, in pcibios_allocate_bus_resources()
655 (unsigned long long)res->end); in pcibios_allocate_bus_resources()
657 (unsigned int)res->flags, in pcibios_allocate_bus_resources()
658 pr, (pr && pr->name) ? pr->name : "nil"); in pcibios_allocate_bus_resources()
660 if (pr && !(pr->flags & IORESOURCE_UNSET)) { in pcibios_allocate_bus_resources()
661 struct pci_dev *dev = bus->self; in pcibios_allocate_bus_resources()
680 pr_cont("%d of PCI bridge %d, will remap\n", i, bus->number); in pcibios_allocate_bus_resources()
681 res->start = res->end = 0; in pcibios_allocate_bus_resources()
682 res->flags = 0; in pcibios_allocate_bus_resources()
685 list_for_each_entry(b, &bus->children, node) in pcibios_allocate_bus_resources()
691 struct resource *pr, *r = &dev->resource[idx]; in alloc_resource()
695 (unsigned long long)r->start, in alloc_resource()
696 (unsigned long long)r->end, in alloc_resource()
697 (unsigned int)r->flags); in alloc_resource()
700 if (!pr || (pr->flags & IORESOURCE_UNSET) || in alloc_resource()
705 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n", in alloc_resource()
707 (unsigned long long)pr->start, in alloc_resource()
708 (unsigned long long)pr->end, in alloc_resource()
709 (unsigned int)pr->flags); in alloc_resource()
711 r->flags |= IORESOURCE_UNSET; in alloc_resource()
712 r->end -= r->start; in alloc_resource()
713 r->start = 0; in alloc_resource()
727 r = &dev->resource[idx]; in pcibios_allocate_resources()
728 if (r->parent) /* Already allocated */ in pcibios_allocate_resources()
730 if (!r->flags || (r->flags & IORESOURCE_UNSET)) in pcibios_allocate_resources()
737 if (r->flags & IORESOURCE_IO) in pcibios_allocate_resources()
746 r = &dev->resource[PCI_ROM_RESOURCE]; in pcibios_allocate_resources()
747 if (r->flags) { in pcibios_allocate_resources()
752 pci_read_config_dword(dev, dev->rom_base_reg, ®); in pcibios_allocate_resources()
756 r->flags &= ~IORESOURCE_ROM_ENABLE; in pcibios_allocate_resources()
757 pci_write_config_dword(dev, dev->rom_base_reg, in pcibios_allocate_resources()
764 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus) in pcibios_reserve_legacy_regions() argument
766 struct pci_controller *hose = pci_bus_to_host(bus); in pcibios_reserve_legacy_regions()
772 pci_domain_nr(bus)); in pcibios_reserve_legacy_regions()
775 if (!(hose->io_resource.flags & IORESOURCE_IO)) in pcibios_reserve_legacy_regions()
777 offset = (unsigned long)hose->io_base_virt - _IO_BASE; in pcibios_reserve_legacy_regions()
780 res->name = "Legacy IO"; in pcibios_reserve_legacy_regions()
781 res->flags = IORESOURCE_IO; in pcibios_reserve_legacy_regions()
782 res->start = offset; in pcibios_reserve_legacy_regions()
783 res->end = (offset + 0xfff) & 0xfffffffful; in pcibios_reserve_legacy_regions()
785 if (request_resource(&hose->io_resource, res)) { in pcibios_reserve_legacy_regions()
787 pci_domain_nr(bus), bus->number, res); in pcibios_reserve_legacy_regions()
793 offset = hose->pci_mem_offset; in pcibios_reserve_legacy_regions()
796 pres = &hose->mem_resources[i]; in pcibios_reserve_legacy_regions()
797 if (!(pres->flags & IORESOURCE_MEM)) in pcibios_reserve_legacy_regions()
800 if ((pres->start - offset) <= 0xa0000 && in pcibios_reserve_legacy_regions()
801 (pres->end - offset) >= 0xbffff) in pcibios_reserve_legacy_regions()
808 res->name = "Legacy VGA memory"; in pcibios_reserve_legacy_regions()
809 res->flags = IORESOURCE_MEM; in pcibios_reserve_legacy_regions()
810 res->start = 0xa0000 + offset; in pcibios_reserve_legacy_regions()
811 res->end = 0xbffff + offset; in pcibios_reserve_legacy_regions()
815 pci_domain_nr(bus), bus->number, res); in pcibios_reserve_legacy_regions()
824 /* Allocate and assign resources. If we re-assign everything, then in pcibios_resource_survey()
835 * bus available resources to avoid allocating things on top of them in pcibios_resource_survey()
853 res = &hose->io_resource; in pcibios_setup_phb_resources()
856 io_offset = (unsigned long)hose->io_base_virt - isa_io_base; in pcibios_setup_phb_resources()
857 res->start = (res->start + io_offset) & 0xffffffffu; in pcibios_setup_phb_resources()
858 res->end = (res->end + io_offset) & 0xffffffffu; in pcibios_setup_phb_resources()
860 if (!res->flags) { in pcibios_setup_phb_resources()
863 hose->dn, hose->global_number); in pcibios_setup_phb_resources()
864 /* Workaround for lack of IO resource only on 32-bit */ in pcibios_setup_phb_resources()
865 res->start = (unsigned long)hose->io_base_virt - isa_io_base; in pcibios_setup_phb_resources()
866 res->end = res->start + IO_SPACE_LIMIT; in pcibios_setup_phb_resources()
867 res->flags = IORESOURCE_IO; in pcibios_setup_phb_resources()
870 (__force resource_size_t)(hose->io_base_virt - _IO_BASE)); in pcibios_setup_phb_resources()
872 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n", in pcibios_setup_phb_resources()
873 (unsigned long long)res->start, in pcibios_setup_phb_resources()
874 (unsigned long long)res->end, in pcibios_setup_phb_resources()
875 (unsigned long)res->flags); in pcibios_setup_phb_resources()
879 res = &hose->mem_resources[i]; in pcibios_setup_phb_resources()
880 if (!res->flags) { in pcibios_setup_phb_resources()
885 hose->dn, hose->global_number); in pcibios_setup_phb_resources()
887 /* Workaround for lack of MEM resource only on 32-bit */ in pcibios_setup_phb_resources()
888 res->start = hose->pci_mem_offset; in pcibios_setup_phb_resources()
889 res->end = (resource_size_t)-1LL; in pcibios_setup_phb_resources()
890 res->flags = IORESOURCE_MEM; in pcibios_setup_phb_resources()
893 pci_add_resource_offset(resources, res, hose->pci_mem_offset); in pcibios_setup_phb_resources()
895 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", in pcibios_setup_phb_resources()
896 i, (unsigned long long)res->start, in pcibios_setup_phb_resources()
897 (unsigned long long)res->end, in pcibios_setup_phb_resources()
898 (unsigned long)res->flags); in pcibios_setup_phb_resources()
902 (unsigned long long)hose->pci_mem_offset); in pcibios_setup_phb_resources()
904 (unsigned long)hose->io_base_virt - _IO_BASE); in pcibios_setup_phb_resources()
910 struct pci_bus *bus; in pcibios_scan_phb() local
911 struct device_node *node = hose->dn; in pcibios_scan_phb()
917 bus = pci_scan_root_bus(hose->parent, hose->first_busno, in pcibios_scan_phb()
918 hose->ops, hose, &resources); in pcibios_scan_phb()
919 if (bus == NULL) { in pcibios_scan_phb()
920 pr_err("Failed to create bus for PCI domain %04x\n", in pcibios_scan_phb()
921 hose->global_number); in pcibios_scan_phb()
925 bus->busn_res.start = hose->first_busno; in pcibios_scan_phb()
926 hose->bus = bus; in pcibios_scan_phb()
928 hose->last_busno = bus->busn_res.end; in pcibios_scan_phb()
940 hose->last_busno = 0xff; in pcibios_init()
942 if (next_busno <= hose->last_busno) in pcibios_init()
943 next_busno = hose->last_busno + 1; in pcibios_init()
950 if (hose->bus) in pcibios_init()
951 pci_bus_add_devices(hose->bus); in pcibios_init()
959 static struct pci_controller *pci_bus_to_hose(int bus) in pci_bus_to_hose() argument
964 if (bus >= hose->first_busno && bus <= hose->last_busno) in pci_bus_to_hose()
970 * memory. Do this on a per-card basis so that we choose the right
975 long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn) in sys_pciconfig_iobase() argument
978 long result = -EOPNOTSUPP; in sys_pciconfig_iobase()
980 hose = pci_bus_to_hose(bus); in sys_pciconfig_iobase()
982 return -ENODEV; in sys_pciconfig_iobase()
986 return (long)hose->first_busno; in sys_pciconfig_iobase()
988 return (long)hose->pci_mem_offset; in sys_pciconfig_iobase()
990 return (long)hose->io_base_phys; in sys_pciconfig_iobase()
1012 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, in null_read_config() argument
1019 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, in null_write_config() argument
1037 static struct pci_bus bus; in fake_pci_bus() local
1040 pr_err("Can't find hose for PCI bus %d!\n", busnr); in fake_pci_bus()
1042 bus.number = busnr; in fake_pci_bus()
1043 bus.sysdata = hose; in fake_pci_bus()
1044 bus.ops = hose ? hose->ops : &null_pci_ops; in fake_pci_bus()
1045 return &bus; in fake_pci_bus()
1049 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1052 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1063 int early_find_capability(struct pci_controller *hose, int bus, int devfn, in EARLY_PCI_OP()
1066 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); in EARLY_PCI_OP()