Lines Matching +full:one +full:- +full:timer +full:- +full:only
1 /* SPDX-License-Identifier: GPL-2.0 */
6 * via them as are assorted bits and bobs - eg rtc, adb. The picture
59 * state-control line SEL" on all but IIfx
83 /* Macintosh Family Hardware sez: bits 0-2 of VIA1A are volume control
85 * On IIci,IIfx, bits 1-2 are the rest of the CPU ID:
89 * CHRP sez: VIA1A bits 0-2 and 5 are 'unused': if programmed as
112 #define VIA1B_vRTCClk 0x02 /* Real time clock serial-clock line. */
113 #define VIA1B_vRTCData 0x01 /* Real time clock serial-data line. */
117 * correspond to a VIA work-alike named 'EVR'. */
132 * defines the 'Video IRQ' as 0x40 for the 'EVR' VIA work-alike.
158 * timer T1.
165 #define VIA2B_vMode32 0x08 /* 24/32bit switch - doubles as cache flush
183 * of the alternate video page for page-flipping animation. Since there
186 * [CSA: don't know which one this is, but it's one of 'em!]
190 * 6522 registers - see databook.
198 #define vBufAH 0x0200 /* [VIA only] Buffer A, with handshake. DON'T USE! */
199 #define vDirB 0x0400 /* [VIA only] Data Direction Register B. */
200 #define vDirA 0x0600 /* [VIA only] Data Direction Register A. */
201 #define vT1CL 0x0800 /* [VIA only] Timer one counter low. */
202 #define vT1CH 0x0a00 /* [VIA only] Timer one counter high. */
203 #define vT1LL 0x0c00 /* [VIA only] Timer one latches low. */
204 #define vT1LH 0x0e00 /* [VIA only] Timer one latches high. */
205 #define vT2CL 0x1000 /* [VIA only] Timer two counter low. */
206 #define vT2CH 0x1200 /* [VIA only] Timer two counter high. */
207 #define vSR 0x1400 /* [VIA only] Shift register. */
208 #define vACR 0x1600 /* [VIA only] Auxiliary control register. */
209 #define vPCR 0x1800 /* [VIA only] Peripheral control register. */
217 /* The RBV only decodes the bottom eight address lines; the VIA doesn't
218 * decode the bottom eight -- so vBufB | rBufB will always get you BufB */
219 /* CSA: in fact, only bits 0,1, and 4 seem to be decoded.
223 * Perhaps some sort of 'compatibility mode' is built-in? [21-May-1999]
227 #define rExp 0x0001 /* [RBV only] RBV future expansion (always 0) */
228 #define rSIFR 0x0002 /* [RBV only] RBV slot interrupts register. */
230 #define rMonP 0x0010 /* [RBV only] RBV video monitor type. */
231 #define rChpT 0x0011 /* [RBV only] RBV test mode register (reads as 0). */
232 #define rSIER 0x0012 /* [RBV only] RBV slot interrupt enables. */
272 char val = (bpp==1)?0:(bpp==2)?1:(bpp==4)?2:(bpp==8)?3:-1; in rbv_set_video_bpp()
273 if (!rbv_present || val<0) return -1; in rbv_set_video_bpp()