Lines Matching +full:tx +full:- +full:enable
4 * m54xxpci.h -- ColdFire 547x and 548x PCI bus support
45 #define PCITPSR (CONFIG_MBAR + 0x8400) /* TX packet size */
46 #define PCITSAR (CONFIG_MBAR + 0x8404) /* TX start address */
47 #define PCITTCR (CONFIG_MBAR + 0x8408) /* TX transaction control */
48 #define PCITER (CONFIG_MBAR + 0x840c) /* TX enables */
49 #define PCITNAR (CONFIG_MBAR + 0x8410) /* TX next address */
50 #define PCITLWR (CONFIG_MBAR + 0x8414) /* TX last word */
51 #define PCITDCR (CONFIG_MBAR + 0x8418) /* TX done counts */
52 #define PCITSR (CONFIG_MBAR + 0x841c) /* TX status */
53 #define PCITFDR (CONFIG_MBAR + 0x8440) /* TX FIFO data */
54 #define PCITFSR (CONFIG_MBAR + 0x8444) /* TX FIFO status */
55 #define PCITFCR (CONFIG_MBAR + 0x8448) /* TX FIFO control */
56 #define PCITFAR (CONFIG_MBAR + 0x844c) /* TX FIFO alarm */
57 #define PCITFRPR (CONFIG_MBAR + 0x8450) /* TX FIFO read pointer */
58 #define PCITFWPR (CONFIG_MBAR + 0x8454) /* TX FIFO write pointer */
83 #define PCIGSCR_PEE 0x00002000 /* Parity error intr enable */
84 #define PCIGSCR_SEE 0x00001000 /* System error intr enable */
90 #define PCICAR_E 0x80000000 /* Enable config space */
101 ((((size) - 1) & 0xff000000) >> 8) | \
109 #define PCIIWCR_W0_E 0x01000000 /* Window 0 enable */
116 #define PCIIWCR_W1_E 0x00010000 /* Window 0 enable */
121 #define PCITBATR0_E 0x00000001 /* Enable window 0 */
122 #define PCITBATR1_E 0x00000001 /* Enable window 1 */