Lines Matching refs:MCF_MBAR
25 #define MCFSIM_SCR (MCF_MBAR + 0x04) /* SIM Config reg */
26 #define MCFSIM_SPR (MCF_MBAR + 0x06) /* System Protection */
27 #define MCFSIM_PMR (MCF_MBAR + 0x08) /* Power Management */
28 #define MCFSIM_APMR (MCF_MBAR + 0x0e) /* Active Low Power */
29 #define MCFSIM_DIR (MCF_MBAR + 0x10) /* Device Identity */
31 #define MCFSIM_ICR1 (MCF_MBAR + 0x20) /* Intr Ctrl reg 1 */
32 #define MCFSIM_ICR2 (MCF_MBAR + 0x24) /* Intr Ctrl reg 2 */
33 #define MCFSIM_ICR3 (MCF_MBAR + 0x28) /* Intr Ctrl reg 3 */
34 #define MCFSIM_ICR4 (MCF_MBAR + 0x2c) /* Intr Ctrl reg 4 */
36 #define MCFSIM_ISR (MCF_MBAR + 0x30) /* Intr Source */
37 #define MCFSIM_PITR (MCF_MBAR + 0x34) /* Intr Transition */
38 #define MCFSIM_PIWR (MCF_MBAR + 0x38) /* Intr Wakeup */
39 #define MCFSIM_PIVR (MCF_MBAR + 0x3f) /* Intr Vector */
41 #define MCFSIM_WRRR (MCF_MBAR + 0x280) /* Watchdog reference */
42 #define MCFSIM_WIRR (MCF_MBAR + 0x284) /* Watchdog interrupt */
43 #define MCFSIM_WCR (MCF_MBAR + 0x288) /* Watchdog counter */
44 #define MCFSIM_WER (MCF_MBAR + 0x28c) /* Watchdog event */
46 #define MCFSIM_CSBR0 (MCF_MBAR + 0x40) /* CS0 Base Address */
47 #define MCFSIM_CSOR0 (MCF_MBAR + 0x44) /* CS0 Option */
48 #define MCFSIM_CSBR1 (MCF_MBAR + 0x48) /* CS1 Base Address */
49 #define MCFSIM_CSOR1 (MCF_MBAR + 0x4c) /* CS1 Option */
50 #define MCFSIM_CSBR2 (MCF_MBAR + 0x50) /* CS2 Base Address */
51 #define MCFSIM_CSOR2 (MCF_MBAR + 0x54) /* CS2 Option */
52 #define MCFSIM_CSBR3 (MCF_MBAR + 0x58) /* CS3 Base Address */
53 #define MCFSIM_CSOR3 (MCF_MBAR + 0x5c) /* CS3 Option */
54 #define MCFSIM_CSBR4 (MCF_MBAR + 0x60) /* CS4 Base Address */
55 #define MCFSIM_CSOR4 (MCF_MBAR + 0x64) /* CS4 Option */
56 #define MCFSIM_CSBR5 (MCF_MBAR + 0x68) /* CS5 Base Address */
57 #define MCFSIM_CSOR5 (MCF_MBAR + 0x6c) /* CS5 Option */
58 #define MCFSIM_CSBR6 (MCF_MBAR + 0x70) /* CS6 Base Address */
59 #define MCFSIM_CSOR6 (MCF_MBAR + 0x74) /* CS6 Option */
60 #define MCFSIM_CSBR7 (MCF_MBAR + 0x78) /* CS7 Base Address */
61 #define MCFSIM_CSOR7 (MCF_MBAR + 0x7c) /* CS7 Option */
63 #define MCFSIM_SDCR (MCF_MBAR + 0x180) /* SDRAM Config */
64 #define MCFSIM_SDTR (MCF_MBAR + 0x184) /* SDRAM Timing */
65 #define MCFSIM_DCAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address */
66 #define MCFSIM_DCMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask */
67 #define MCFSIM_DCCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control */
68 #define MCFSIM_DCAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address */
69 #define MCFSIM_DCMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg */
70 #define MCFSIM_DCCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control */
72 #define MCFUART_BASE0 (MCF_MBAR + 0x100) /* Base address UART0 */
73 #define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */
75 #define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */
76 #define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */
77 #define MCFSIM_PADAT (MCF_MBAR + 0x86) /* Port A Data (r/w) */
78 #define MCFSIM_PBCNT (MCF_MBAR + 0x88) /* Port B Control (r/w) */
79 #define MCFSIM_PBDDR (MCF_MBAR + 0x8c) /* Port B Direction (r/w) */
80 #define MCFSIM_PBDAT (MCF_MBAR + 0x8e) /* Port B Data (r/w) */
81 #define MCFSIM_PCDDR (MCF_MBAR + 0x94) /* Port C Direction (r/w) */
82 #define MCFSIM_PCDAT (MCF_MBAR + 0x96) /* Port C Data (r/w) */
83 #define MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */
85 #define MCFDMA_BASE0 (MCF_MBAR + 0xe0) /* Base address DMA 0 */
87 #define MCFTIMER_BASE1 (MCF_MBAR + 0x200) /* Base address TIMER1 */
88 #define MCFTIMER_BASE2 (MCF_MBAR + 0x220) /* Base address TIMER2 */
89 #define MCFTIMER_BASE3 (MCF_MBAR + 0x240) /* Base address TIMER4 */
90 #define MCFTIMER_BASE4 (MCF_MBAR + 0x260) /* Base address TIMER3 */
92 #define MCFFEC_BASE0 (MCF_MBAR + 0x840) /* Base FEC ethernet */