Lines Matching +full:0 +full:xfffff0
26 * 0xFFFFF0xx -- System Control
33 #define SCR_ADDR 0xfffff000
36 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
37 #define SCR_DMAP 0x04 /* Double Map */
38 #define SCR_SO 0x08 /* Supervisor Only */
39 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
40 #define SCR_PRV 0x20 /* Privilege Violation */
41 #define SCR_WPV 0x40 /* Write Protect Violation */
42 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
47 #define MRR_ADDR 0xfffff004
52 * 0xFFFFF1xx -- Chip-Select logic
58 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
65 #define GRPBASEA_ADDR 0xfffff100
66 #define GRPBASEB_ADDR 0xfffff102
67 #define GRPBASEC_ADDR 0xfffff104
68 #define GRPBASED_ADDR 0xfffff106
75 #define GRPBASE_V 0x0001 /* Valid */
76 #define GRPBASE_GBA_MASK 0xfff0 /* Group Base Address (bits 31-20) */
81 #define GRPMASKA_ADDR 0xfffff108
82 #define GRPMASKB_ADDR 0xfffff10a
83 #define GRPMASKC_ADDR 0xfffff10c
84 #define GRPMASKD_ADDR 0xfffff10e
91 #define GRMMASK_GMA_MASK 0xfffff0 /* Group Base Mask (bits 31-20) */
96 #define CSA0_ADDR 0xfffff110
97 #define CSA1_ADDR 0xfffff114
98 #define CSA2_ADDR 0xfffff118
99 #define CSA3_ADDR 0xfffff11c
106 #define CSA_WAIT_MASK 0x00000007 /* Wait State Selection */
107 #define CSA_WAIT_SHIFT 0
108 #define CSA_RO 0x00000008 /* Read-Only */
109 #define CSA_AM_MASK 0x0000ff00 /* Address Mask (bits 23-16) */
111 #define CSA_BUSW 0x00010000 /* Bus Width Select */
112 #define CSA_AC_MASK 0xff000000 /* Address Compare (bits 23-16) */
118 #define CSB0_ADDR 0xfffff120
119 #define CSB1_ADDR 0xfffff124
120 #define CSB2_ADDR 0xfffff128
121 #define CSB3_ADDR 0xfffff12c
128 #define CSB_WAIT_MASK 0x00000007 /* Wait State Selection */
129 #define CSB_WAIT_SHIFT 0
130 #define CSB_RO 0x00000008 /* Read-Only */
131 #define CSB_AM_MASK 0x0000ff00 /* Address Mask (bits 23-16) */
133 #define CSB_BUSW 0x00010000 /* Bus Width Select */
134 #define CSB_AC_MASK 0xff000000 /* Address Compare (bits 23-16) */
140 #define CSC0_ADDR 0xfffff130
141 #define CSC1_ADDR 0xfffff134
142 #define CSC2_ADDR 0xfffff138
143 #define CSC3_ADDR 0xfffff13c
150 #define CSC_WAIT_MASK 0x00000007 /* Wait State Selection */
151 #define CSC_WAIT_SHIFT 0
152 #define CSC_RO 0x00000008 /* Read-Only */
153 #define CSC_AM_MASK 0x0000fff0 /* Address Mask (bits 23-12) */
155 #define CSC_BUSW 0x00010000 /* Bus Width Select */
156 #define CSC_AC_MASK 0xfff00000 /* Address Compare (bits 23-12) */
162 #define CSD0_ADDR 0xfffff140
163 #define CSD1_ADDR 0xfffff144
164 #define CSD2_ADDR 0xfffff148
165 #define CSD3_ADDR 0xfffff14c
172 #define CSD_WAIT_MASK 0x00000007 /* Wait State Selection */
173 #define CSD_WAIT_SHIFT 0
174 #define CSD_RO 0x00000008 /* Read-Only */
175 #define CSD_AM_MASK 0x0000fff0 /* Address Mask (bits 23-12) */
177 #define CSD_BUSW 0x00010000 /* Bus Width Select */
178 #define CSD_AC_MASK 0xfff00000 /* Address Compare (bits 23-12) */
183 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
190 #define PLLCR_ADDR 0xfffff200
193 #define PLLCR_DISPLL 0x0008 /* Disable PLL */
194 #define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */
195 #define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */
197 #define PLLCR_PIXCLK_SEL_MASK 0x3800 /* LCD Clock Selection */
207 #define PLLFSR_ADDR 0xfffff202
210 #define PLLFSR_PC_MASK 0x00ff /* P Count */
211 #define PLLFSR_PC_SHIFT 0
212 #define PLLFSR_QC_MASK 0x0f00 /* Q Count */
214 #define PLLFSR_PROT 0x4000 /* Protect P & Q */
215 #define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */
220 #define PCTRL_ADDR 0xfffff207
223 #define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */
224 #define PCTRL_WIDTH_SHIFT 0
225 #define PCTRL_STOP 0x40 /* Enter power-save mode immediately */
226 #define PCTRL_PCEN 0x80 /* Power Control Enable */
230 * 0xFFFFF3xx -- Interrupt Controller
237 #define IVR_ADDR 0xfffff300
240 #define IVR_VECTOR_MASK 0xF8
245 #define ICR_ADRR 0xfffff302
248 #define ICR_ET6 0x0100 /* Edge Trigger Select for IRQ6 */
249 #define ICR_ET3 0x0200 /* Edge Trigger Select for IRQ3 */
250 #define ICR_ET2 0x0400 /* Edge Trigger Select for IRQ2 */
251 #define ICR_ET1 0x0800 /* Edge Trigger Select for IRQ1 */
252 #define ICR_POL6 0x1000 /* Polarity Control for IRQ6 */
253 #define ICR_POL3 0x2000 /* Polarity Control for IRQ3 */
254 #define ICR_POL2 0x4000 /* Polarity Control for IRQ2 */
255 #define ICR_POL1 0x8000 /* Polarity Control for IRQ1 */
260 #define IMR_ADDR 0xfffff304
267 #define SPIM_IRQ_NUM 0 /* SPI Master interrupt */
329 #define IWR_ADDR 0xfffff308
359 #define ISR_ADDR 0xfffff30c
393 #define IPR_ADDR 0xfffff310
426 * 0xFFFFF4xx -- Parallel Ports
433 #define PADIR_ADDR 0xfffff400 /* Port A direction reg */
434 #define PADATA_ADDR 0xfffff401 /* Port A data register */
435 #define PASEL_ADDR 0xfffff403 /* Port A Select register */
444 #define PA_A16 PA(0) /* Use A16 as PA(0) */
456 #define PBDIR_ADDR 0xfffff408 /* Port B direction reg */
457 #define PBDATA_ADDR 0xfffff409 /* Port B data register */
458 #define PBSEL_ADDR 0xfffff40b /* Port B Select Register */
467 #define PB_D0 PB(0) /* Use D0 as PB(0) */
479 #define PCDIR_ADDR 0xfffff410 /* Port C direction reg */
480 #define PCDATA_ADDR 0xfffff411 /* Port C data register */
481 #define PCSEL_ADDR 0xfffff413 /* Port C Select Register */
494 #define PC_MOCLK PC(0) /* Use MOCLK as PC(0) */
499 #define PDDIR_ADDR 0xfffff418 /* Port D direction reg */
500 #define PDDATA_ADDR 0xfffff419 /* Port D data register */
501 #define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */
502 #define PDPOL_ADDR 0xfffff41c /* Port D Polarity Register */
503 #define PDIRQEN_ADDR 0xfffff41d /* Port D IRQ enable register */
504 #define PDIQEG_ADDR 0xfffff41f /* Port D IRQ Edge Register */
516 #define PD_KB0 PD(0) /* Use KB0 as PD(0) */
528 #define PEDIR_ADDR 0xfffff420 /* Port E direction reg */
529 #define PEDATA_ADDR 0xfffff421 /* Port E data register */
530 #define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */
531 #define PESEL_ADDR 0xfffff423 /* Port E Select Register */
551 #define PFDIR_ADDR 0xfffff428 /* Port F direction reg */
552 #define PFDATA_ADDR 0xfffff429 /* Port F data register */
553 #define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */
554 #define PFSEL_ADDR 0xfffff42b /* Port F Select Register */
564 #define PF_A24 PF(0) /* Use A24 as PF(0) */
576 #define PGDIR_ADDR 0xfffff430 /* Port G direction reg */
577 #define PGDATA_ADDR 0xfffff431 /* Port G data register */
578 #define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */
579 #define PGSEL_ADDR 0xfffff433 /* Port G Select Register */
588 #define PG_UART_TXD PG(0) /* Use UART_TXD as PG(0) */
600 #define PJDIR_ADDR 0xfffff438 /* Port J direction reg */
601 #define PJDATA_ADDR 0xfffff439 /* Port J data register */
602 #define PJSEL_ADDR 0xfffff43b /* Port J Select Register */
615 #define PKDIR_ADDR 0xfffff440 /* Port K direction reg */
616 #define PKDATA_ADDR 0xfffff441 /* Port K data register */
617 #define PKPUEN_ADDR 0xfffff442 /* Port K Pull-Up enable reg */
618 #define PKSEL_ADDR 0xfffff443 /* Port K Select Register */
630 #define PMDIR_ADDR 0xfffff438 /* Port M direction reg */
631 #define PMDATA_ADDR 0xfffff439 /* Port M data register */
632 #define PMPUEN_ADDR 0xfffff43a /* Port M Pull-Up enable reg */
633 #define PMSEL_ADDR 0xfffff43b /* Port M Select Register */
644 * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
651 #define PWMC_ADDR 0xfffff500
654 #define PWMC_CLKSEL_MASK 0x0007 /* Clock Selection */
655 #define PWMC_CLKSEL_SHIFT 0
656 #define PWMC_PWMEN 0x0010 /* Enable PWM */
657 #define PMNC_POL 0x0020 /* PWM Output Bit Polarity */
658 #define PWMC_PIN 0x0080 /* Current PWM output pin status */
659 #define PWMC_LOAD 0x0100 /* Force a new period */
660 #define PWMC_IRQEN 0x4000 /* Interrupt Request Enable */
661 #define PWMC_CLKSRC 0x8000 /* Clock Source Select */
669 #define PWMP_ADDR 0xfffff502
675 #define PWMW_ADDR 0xfffff504
681 #define PWMCNT_ADDR 0xfffff506
686 * 0xFFFFF6xx -- General-Purpose Timers
693 #define TCTL1_ADDR 0xfffff600
695 #define TCTL2_ADDR 0xfffff60c
698 #define TCTL_TEN 0x0001 /* Timer Enable */
699 #define TCTL_CLKSOURCE_MASK 0x000e /* Clock Source: */
700 #define TCTL_CLKSOURCE_STOP 0x0000 /* Stop count (disabled) */
701 #define TCTL_CLKSOURCE_SYSCLK 0x0002 /* SYSCLK to prescaler */
702 #define TCTL_CLKSOURCE_SYSCLK_16 0x0004 /* SYSCLK/16 to prescaler */
703 #define TCTL_CLKSOURCE_TIN 0x0006 /* TIN to prescaler */
704 #define TCTL_CLKSOURCE_32KHZ 0x0008 /* 32kHz clock to prescaler */
705 #define TCTL_IRQEN 0x0010 /* IRQ Enable */
706 #define TCTL_OM 0x0020 /* Output Mode */
707 #define TCTL_CAP_MASK 0x00c0 /* Capture Edge: */
708 #define TCTL_CAP_RE 0x0040 /* Capture on rizing edge */
709 #define TCTL_CAP_FE 0x0080 /* Capture on falling edge */
710 #define TCTL_FRR 0x0010 /* Free-Run Mode */
719 #define TPRER1_ADDR 0xfffff602
721 #define TPRER2_ADDR 0xfffff60e
731 #define TCMP1_ADDR 0xfffff604
733 #define TCMP2_ADDR 0xfffff610
743 #define TCR1_ADDR 0xfffff606
745 #define TCR2_ADDR 0xfffff612
755 #define TCN1_ADDR 0xfffff608
757 #define TCN2_ADDR 0xfffff614
767 #define TSTAT1_ADDR 0xfffff60a
769 #define TSTAT2_ADDR 0xfffff616
772 #define TSTAT_COMP 0x0001 /* Compare Event occurred */
773 #define TSTAT_CAPT 0x0001 /* Capture Event occurred */
782 #define WRR_ADDR 0xfffff61a
788 #define WCN_ADDR 0xfffff61c
794 #define WCSR_ADDR 0xfffff618
797 #define WCSR_WDEN 0x0001 /* Watchdog Enable */
798 #define WCSR_FI 0x0002 /* Forced Interrupt (instead of SW reset)*/
799 #define WCSR_WRST 0x0004 /* Watchdog Reset */
803 * 0xFFFFF7xx -- Serial Peripheral Interface Slave (SPIS)
810 #define SPISR_ADDR 0xfffff700
813 #define SPISR_DATA_ADDR 0xfffff701
816 #define SPISR_DATA_MASK 0x00ff /* Shifted data from the external device */
817 #define SPISR_DATA_SHIFT 0
818 #define SPISR_SPISEN 0x0100 /* SPIS module enable */
819 #define SPISR_POL 0x0200 /* SPSCLK polarity control */
820 #define SPISR_PHA 0x0400 /* Phase relationship between SPSCLK & SPSRxD */
821 #define SPISR_OVWR 0x0800 /* Data buffer has been overwritten */
822 #define SPISR_DATARDY 0x1000 /* Data ready */
823 #define SPISR_ENPOL 0x2000 /* Enable Polarity */
824 #define SPISR_IRQEN 0x4000 /* SPIS IRQ Enable */
825 #define SPISR_SPISIRQ 0x8000 /* SPIS IRQ posted */
829 * 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
836 #define SPIMDATA_ADDR 0xfffff800
842 #define SPIMCONT_ADDR 0xfffff802
845 #define SPIMCONT_BIT_COUNT_MASK 0x000f /* Transfer Length in Bytes */
846 #define SPIMCONT_BIT_COUNT_SHIFT 0
847 #define SPIMCONT_POL 0x0010 /* SPMCLK Signel Polarity */
848 #define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */
849 #define SPIMCONT_IRQEN 0x0040 /* IRQ Enable */
850 #define SPIMCONT_SPIMIRQ 0x0080 /* Interrupt Request */
851 #define SPIMCONT_XCH 0x0100 /* Exchange */
852 #define SPIMCONT_RSPIMEN 0x0200 /* Enable SPIM */
853 #define SPIMCONT_DATA_RATE_MASK 0xe000 /* SPIM Data Rate */
861 * 0xFFFFF9xx -- UART
868 #define USTCNT_ADDR 0xfffff900
871 #define USTCNT_TXAVAILEN 0x0001 /* Transmitter Available Int Enable */
872 #define USTCNT_TXHALFEN 0x0002 /* Transmitter Half Empty Int Enable */
873 #define USTCNT_TXEMPTYEN 0x0004 /* Transmitter Empty Int Enable */
874 #define USTCNT_RXREADYEN 0x0008 /* Receiver Ready Interrupt Enable */
875 #define USTCNT_RXHALFEN 0x0010 /* Receiver Half-Full Int Enable */
876 #define USTCNT_RXFULLEN 0x0020 /* Receiver Full Interrupt Enable */
877 #define USTCNT_CTSDELTAEN 0x0040 /* CTS Delta Interrupt Enable */
878 #define USTCNT_GPIODELTAEN 0x0080 /* Old Data Interrupt Enable */
879 #define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */
880 #define USTCNT_STOP 0x0200 /* Stop bit transmission */
881 #define USTCNT_ODD_EVEN 0x0400 /* Odd Parity */
882 #define USTCNT_PARITYEN 0x0800 /* Parity Enable */
883 #define USTCNT_CLKMODE 0x1000 /* Clock Mode Select */
884 #define USTCNT_TXEN 0x2000 /* Transmitter Enable */
885 #define USTCNT_RXEN 0x4000 /* Receiver Enable */
886 #define USTCNT_UARTEN 0x8000 /* UART Enable */
904 #define UBAUD_ADDR 0xfffff902
907 #define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */
908 #define UBAUD_PRESCALER_SHIFT 0
909 #define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divisor */
911 #define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */
912 #define UBAUD_GPIOSRC 0x1000 /* GPIO source */
913 #define UBAUD_GPIODIR 0x2000 /* GPIO Direction */
914 #define UBAUD_GPIO 0x4000 /* Current GPIO pin status */
915 #define UBAUD_GPIODELTA 0x8000 /* GPIO pin value changed */
920 #define URX_ADDR 0xfffff904
923 #define URX_RXDATA_ADDR 0xfffff905
926 #define URX_RXDATA_MASK 0x00ff /* Received data */
927 #define URX_RXDATA_SHIFT 0
928 #define URX_PARITY_ERROR 0x0100 /* Parity Error */
929 #define URX_BREAK 0x0200 /* Break Detected */
930 #define URX_FRAME_ERROR 0x0400 /* Framing Error */
931 #define URX_OVRUN 0x0800 /* Serial Overrun */
932 #define URX_DATA_READY 0x2000 /* Data Ready (FIFO not empty) */
933 #define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */
934 #define URX_FIFO_FULL 0x8000 /* FIFO is Full */
939 #define UTX_ADDR 0xfffff906
942 #define UTX_TXDATA_ADDR 0xfffff907
945 #define UTX_TXDATA_MASK 0x00ff /* Data to be transmitted */
946 #define UTX_TXDATA_SHIFT 0
947 #define UTX_CTS_DELTA 0x0100 /* CTS changed */
948 #define UTX_CTS_STATUS 0x0200 /* CTS State */
949 #define UTX_IGNORE_CTS 0x0800 /* Ignore CTS */
950 #define UTX_SEND_BREAK 0x1000 /* Send a BREAK */
951 #define UTX_TX_AVAIL 0x2000 /* Transmit FIFO has a slot available */
952 #define UTX_FIFO_HALF 0x4000 /* Transmit FIFO is half empty */
953 #define UTX_FIFO_EMPTY 0x8000 /* Transmit FIFO is empty */
962 #define UMISC_ADDR 0xfffff908
965 #define UMISC_TX_POL 0x0004 /* Transmit Polarity */
966 #define UMISC_RX_POL 0x0008 /* Receive Polarity */
967 #define UMISC_IRDA_LOOP 0x0010 /* IrDA Loopback Enable */
968 #define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */
969 #define UMISC_RTS 0x0040 /* Set RTS status */
970 #define UMISC_RTSCONT 0x0080 /* Choose RTS control */
971 #define UMISC_LOOP 0x1000 /* Serial Loopback Enable */
972 #define UMISC_FORCE_PERR 0x2000 /* Force Parity Error */
973 #define UMISC_CLKSRC 0x4000 /* Clock Source */
1003 * 0xFFFFFAxx -- LCD Controller
1010 #define LSSA_ADDR 0xfffffa00
1013 #define LSSA_SSA_MASK 0xfffffffe /* Bit 0 is reserved */
1018 #define LVPW_ADDR 0xfffffa05
1024 #define LXMAX_ADDR 0xfffffa08
1027 #define LXMAX_XM_MASK 0x02ff /* Bits 0-3 are reserved */
1032 #define LYMAX_ADDR 0xfffffa0a
1035 #define LYMAX_YM_MASK 0x02ff /* Bits 10-15 are reserved */
1040 #define LCXP_ADDR 0xfffffa18
1043 #define LCXP_CC_MASK 0xc000 /* Cursor Control */
1044 #define LCXP_CC_TRAMSPARENT 0x0000
1045 #define LCXP_CC_BLACK 0x4000
1046 #define LCXP_CC_REVERSED 0x8000
1047 #define LCXP_CC_WHITE 0xc000
1048 #define LCXP_CXP_MASK 0x02ff /* Cursor X position */
1053 #define LCYP_ADDR 0xfffffa1a
1056 #define LCYP_CYP_MASK 0x01ff /* Cursor Y Position */
1061 #define LCWCH_ADDR 0xfffffa1c
1064 #define LCWCH_CH_MASK 0x001f /* Cursor Height */
1065 #define LCWCH_CH_SHIFT 0
1066 #define LCWCH_CW_MASK 0x1f00 /* Cursor Width */
1072 #define LBLKC_ADDR 0xfffffa1f
1075 #define LBLKC_BD_MASK 0x7f /* Blink Divisor */
1076 #define LBLKC_BD_SHIFT 0
1077 #define LBLKC_BKEN 0x80 /* Blink Enabled */
1082 #define LPICF_ADDR 0xfffffa20
1085 #define LPICF_GS_MASK 0x01 /* Gray-Scale Mode */
1086 #define LPICF_GS_BW 0x00
1087 #define LPICF_GS_GRAY_4 0x01
1088 #define LPICF_PBSIZ_MASK 0x06 /* Panel Bus Width */
1089 #define LPICF_PBSIZ_1 0x00
1090 #define LPICF_PBSIZ_2 0x02
1091 #define LPICF_PBSIZ_4 0x04
1096 #define LPOLCF_ADDR 0xfffffa21
1099 #define LPOLCF_PIXPOL 0x01 /* Pixel Polarity */
1100 #define LPOLCF_LPPOL 0x02 /* Line Pulse Polarity */
1101 #define LPOLCF_FLMPOL 0x04 /* Frame Marker Polarity */
1102 #define LPOLCF_LCKPOL 0x08 /* LCD Shift Lock Polarity */
1107 #define LACDRC_ADDR 0xfffffa23
1110 #define LACDRC_ACD_MASK 0x0f /* Alternate Crystal Direction Control */
1111 #define LACDRC_ACD_SHIFT 0
1116 #define LPXCD_ADDR 0xfffffa25
1119 #define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */
1120 #define LPXCD_PCD_SHIFT 0
1125 #define LCKCON_ADDR 0xfffffa27
1128 #define LCKCON_PCDS 0x01 /* Pixel Clock Divider Source Select */
1129 #define LCKCON_DWIDTH 0x02 /* Display Memory Width */
1130 #define LCKCON_DWS_MASK 0x3c /* Display Wait-State */
1132 #define LCKCON_DMA16 0x40 /* DMA burst length */
1133 #define LCKCON_LCDON 0x80 /* Enable LCD Controller */
1142 #define LLBAR_ADDR 0xfffffa29
1145 #define LLBAR_LBAR_MASK 0x7f /* Number of memory words to fill 1 line */
1146 #define LLBAR_LBAR_SHIFT 0
1151 #define LOTCR_ADDR 0xfffffa2b
1157 #define LPOSR_ADDR 0xfffffa2d
1160 #define LPOSR_BOS 0x08 /* Byte offset (for B/W mode only */
1161 #define LPOSR_POS_MASK 0x07 /* Pixel Offset Code */
1162 #define LPOSR_POS_SHIFT 0
1167 #define LFRCM_ADDR 0xfffffa31
1170 #define LFRCM_YMOD_MASK 0x0f /* Vertical Modulation */
1171 #define LFRCM_YMOD_SHIFT 0
1172 #define LFRCM_XMOD_MASK 0xf0 /* Horizontal Modulation */
1178 #define LGPMR_ADDR 0xfffffa32
1181 #define LGPMR_GLEVEL3_MASK 0x000f
1182 #define LGPMR_GLEVEL3_SHIFT 0
1183 #define LGPMR_GLEVEL2_MASK 0x00f0
1185 #define LGPMR_GLEVEL0_MASK 0x0f00
1187 #define LGPMR_GLEVEL1_MASK 0xf000
1192 * 0xFFFFFBxx -- Real-Time Clock (RTC)
1199 #define RTCTIME_ADDR 0xfffffb00
1202 #define RTCTIME_SECONDS_MASK 0x0000003f /* Seconds */
1203 #define RTCTIME_SECONDS_SHIFT 0
1204 #define RTCTIME_MINUTES_MASK 0x003f0000 /* Minutes */
1206 #define RTCTIME_HOURS_MASK 0x1f000000 /* Hours */
1212 #define RTCALRM_ADDR 0xfffffb04
1215 #define RTCALRM_SECONDS_MASK 0x0000003f /* Seconds */
1216 #define RTCALRM_SECONDS_SHIFT 0
1217 #define RTCALRM_MINUTES_MASK 0x003f0000 /* Minutes */
1219 #define RTCALRM_HOURS_MASK 0x1f000000 /* Hours */
1225 #define RTCCTL_ADDR 0xfffffb0c
1228 #define RTCCTL_384 0x0020 /* Crystal Selection */
1229 #define RTCCTL_ENABLE 0x0080 /* RTC Enable */
1238 #define RTCISR_ADDR 0xfffffb0e
1241 #define RTCISR_SW 0x0001 /* Stopwatch timed out */
1242 #define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */
1243 #define RTCISR_ALM 0x0004 /* Alarm interrupt has occurred */
1244 #define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */
1245 #define RTCISR_1HZ 0x0010 /* 1Hz interrupt has occurred */
1250 #define RTCIENR_ADDR 0xfffffb10
1253 #define RTCIENR_SW 0x0001 /* Stopwatch interrupt enable */
1254 #define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */
1255 #define RTCIENR_ALM 0x0004 /* Alarm interrupt enable */
1256 #define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */
1257 #define RTCIENR_1HZ 0x0010 /* 1Hz interrupt enable */
1262 #define STPWCH_ADDR 0xfffffb12
1265 #define STPWCH_CNT_MASK 0x00ff /* Stopwatch countdown value */
1266 #define SPTWCH_CNT_SHIFT 0