Lines Matching full:d1
644 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
699 mov.b 1+EXC_CMDREG(%a6),%d1
700 andi.w &0x007f,%d1 # extract extension
711 mov.l (tbl_unsupp.l,%pc,%d1.w*4),%d1 # fetch routine addr
712 jsr (tbl_unsupp.l,%pc,%d1.l*1)
732 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
747 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
766 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
805 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
884 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
942 mov.b 1+EXC_CMDREG(%a6),%d1
943 andi.w &0x007f,%d1 # extract extension
954 mov.l (tbl_unsupp.l,%pc,%d1.w*4),%d1 # fetch routine addr
955 jsr (tbl_unsupp.l,%pc,%d1.l*1)
982 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1009 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1040 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1079 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1209 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
1300 bfextu 1+EXC_CMDREG(%a6){&1:&7},%d1 # extract extension
1305 mov.l (tbl_unsupp.l,%pc,%d1.l*4),%d1 # fetch routine addr
1306 jsr (tbl_unsupp.l,%pc,%d1.l*1)
1339 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1406 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1571 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1595 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1678 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1693 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1710 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1739 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1763 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1791 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1845 bfextu 1+EXC_CMDREG(%a6){&1:&7},%d1 # extract extension
1850 mov.l (tbl_unsupp.l,%pc,%d1.l*4),%d1 # fetch routine addr
1851 jsr (tbl_unsupp.l,%pc,%d1.l*1)
1891 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1909 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1990 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2021 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2122 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2140 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2190 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2230 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2270 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2317 mov.l FP_SRC_HI(%a6),%d1 # fetch DENORM hi(man)
2318 lsr.l %d0,%d1 # shift it
2319 bset &31,%d1 # set j-bit
2320 mov.l %d1,FP_SRC_HI(%a6) # insert new hi(man)
2338 mov.w &0x3c01,%d1 # pass denorm threshold
2358 clr.l %d1
2465 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
2513 tst.l %d1 # did ifetch fail?
2525 tst.l %d1 # did ifetch fail?
2593 mov.b 1+EXC_CMDREG(%a6),%d1
2594 andi.w &0x007f,%d1 # extract extension
2602 mov.l (tbl_unsupp.l,%pc,%d1.w*4),%d1 # fetch routine addr
2603 jsr (tbl_unsupp.l,%pc,%d1.l*1)
2638 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2698 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2780 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2797 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2803 # right now, d1 = size and d0 = the strg.
2805 mov.b %d1,EXC_VOFF(%a6) # store strg
2810 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2814 mov.l %d1,-(%sp) # save d1
2840 clr.l %d1
2841 mov.b EXC_VOFF(%a6),%d1 # fetch strg
2843 tst.b %d1
2848 lsl.b &0x1,%d1
2853 lsl.b &0x1,%d1
2858 lsl.b &0x1,%d1
2863 lsl.b &0x1,%d1
2868 lsl.b &0x1,%d1
2873 lsl.b &0x1,%d1
2878 lsl.b &0x1,%d1
2882 mov.l 0x4(%sp),%d1
2899 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2954 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
2974 bfextu %d0{&19:&3},%d1
2976 cmpi.b %d1,&0x7 # move all regs?
2992 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
3021 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
3043 movc %pcr,%d1
3044 btst &0x1,%d1
3058 movm.l LOCAL_SIZE+EXC_DREGS(%sp),&0x0303 # restore d0-d1/a0-a1
3112 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
3140 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
3166 mov.w FP_SRC_EX(%a6),%d1 # fetch exponent
3167 andi.w &0x7fff,%d1
3168 cmpi.w %d1,&0x7fff
3173 mov.l FP_SRC_HI(%a6),%d1
3174 andi.l &0x7fffffff,%d1
3181 mov.l &0x7fffffff,%d1
3184 addq.l &0x1,%d1
3186 mov.l %d1,L_SCR1(%a6)
3190 mov.b 1+EXC_OPWORD(%a6),%d1 # extract <ea> mode,reg
3206 cmpi.b %d1,&0x7 # is <ea> mode a data reg?
3211 tst.l %d1 # did dstore fail?
3216 andi.w &0x0007,%d1
3222 cmpi.b %d1,&0x7 # is <ea> mode a data reg?
3227 tst.l %d1 # did dstore fail?
3232 andi.w &0x0007,%d1
3238 cmpi.b %d1,&0x7 # is <ea> mode a data reg?
3243 tst.l %d1 # did dstore fail?
3248 andi.w &0x0007,%d1
3308 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
3336 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
3360 mov.b 1+EXC_OPWORD(%a6),%d1 # extract <ea> mode,reg
3377 cmpi.b %d1,&0x7 # is <ea> mode a data reg?
3382 tst.l %d1 # did dstore fail?
3387 andi.w &0x0007,%d1
3394 cmpi.b %d1,&0x7 # is <ea> mode a data reg?
3399 tst.l %d1 # did dstore fail?
3404 andi.w &0x0007,%d1
3411 cmpi.b %d1,&0x7 # is <ea> mode a data reg?
3416 tst.l %d1 # did dstore fail?
3421 andi.w &0x0007,%d1
3426 cmpi.b %d1,&0x7 # is <ea> mode a data reg?
3431 mov.l FP_SRC_HI(%a6),%d1 # load mantissa
3432 lsr.l &0x8,%d1 # shift mantissa for sgl
3433 or.l %d1,%d0 # create sgl SNAN
3437 tst.l %d1 # did dstore fail?
3445 mov.l %d1,-(%sp)
3446 mov.l FP_SRC_HI(%a6),%d1 # load mantissa
3447 lsr.l &0x8,%d1 # shift mantissa for sgl
3448 or.l %d1,%d0 # create sgl SNAN
3449 mov.l (%sp)+,%d1
3450 andi.w &0x0007,%d1
3458 mov.l FP_SRC_HI(%a6),%d1 # load hi mantissa
3461 lsr.l %d0,%d1
3462 or.l %d1,FP_SCR0_EX(%a6) # create dbl hi
3463 mov.l FP_SRC_HI(%a6),%d1 # load hi mantissa
3464 andi.l &0x000007ff,%d1
3465 ror.l %d0,%d1
3466 mov.l %d1,FP_SCR0_HI(%a6) # store to temp space
3467 mov.l FP_SRC_LO(%a6),%d1 # load lo mantissa
3468 lsr.l %d0,%d1
3469 or.l %d1,FP_SCR0_HI(%a6) # create dbl lo
3475 tst.l %d1 # did dstore fail?
3513 tst.l %d1 # did dstore fail?
3533 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
3600 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
3644 bfextu EXC_EXTWORD(%a6){&0:&6},%d1 # extract upper 6 of cmdreg
3645 cmpi.b %d1,&0x17 # is op an fmovecr?
3676 mov.b 1+EXC_CMDREG(%a6),%d1
3677 andi.w &0x007f,%d1 # extract extension
3682 mov.l (tbl_unsupp.l,%pc,%d1.w*4),%d1 # fetch routine addr
3683 jsr (tbl_unsupp.l,%pc,%d1.l*1)
3693 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
3703 mov.b 1+EXC_CMDREG(%a6),%d1
3704 andi.l &0x0000007f,%d1 # pass rom offset
3774 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
3798 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
3880 mov.l %d0, %d1 # make a copy
3883 andi.l &0x7, %d1 # extract reg field
3891 or.w %d1,%d0 # concat mode,reg
3963 mov.l %d0,%d1 # make a copy
3966 andi.l &0x7,%d1 # extract reg field
3981 mov.w (tbl_ceaf_pi.b,%pc,%d1.w*2),%d1
3983 jmp (tbl_ceaf_pi.b,%pc,%d1.w*1)
4026 mov.w (tbl_ceaf_pd.b,%pc,%d1.w*2),%d1
4030 jmp (tbl_ceaf_pd.b,%pc,%d1.w*1)
4215 # d1 = Dn #
4268 mov.b 1+EXC_EXTWORD(%a6),%d1 # fetch extword
4269 andi.w &0x70,%d1 # extract reg bits
4270 lsr.b &0x4,%d1 # shift into lo bits
4282 mov.l (%sp)+,%d1 # restore strg
4304 mov.b (tbl_fmovm_convert.w,%pc,%d1.w*1),%d1
4325 tst.b %d1 # should FP0 be moved?
4333 lsl.b &0x1,%d1 # should FP1 be moved?
4341 lsl.b &0x1,%d1 # should FP2 be moved?
4348 lsl.b &0x1,%d1 # should FP3 be moved?
4355 lsl.b &0x1,%d1 # should FP4 be moved?
4362 lsl.b &0x1,%d1 # should FP5 be moved?
4369 lsl.b &0x1,%d1 # should FP6 be moved?
4376 lsl.b &0x1,%d1 # should FP7 be moved?
4392 tst.l %d1 # did dstore err?
4406 mov.l %d1,-(%sp) # save bit string for later
4413 tst.l %d1 # did dfetch fail?
4416 mov.l (%sp)+,%d1 # load bit string
4420 tst.b %d1 # should FP0 be moved?
4428 lsl.b &0x1,%d1 # should FP1 be moved?
4436 lsl.b &0x1,%d1 # should FP2 be moved?
4442 lsl.b &0x1,%d1 # should FP3 be moved?
4448 lsl.b &0x1,%d1 # should FP4 be moved?
4454 lsl.b &0x1,%d1 # should FP5 be moved?
4460 lsl.b &0x1,%d1 # should FP6 be moved?
4466 lsl.b &0x1,%d1 # should FP7 be moved?
4578 mov.w %d0,%d1 # make a copy
4581 andi.l &0x7,%d1 # extract reg field
4701 mov.l %d0,%d1
4702 add.l %a0,%d1 # Increment
4703 mov.l %d1,EXC_DREGS+0x8(%a6) # Save incr value
4709 mov.l %d0,%d1
4710 add.l %a0,%d1 # Increment
4711 mov.l %d1,EXC_DREGS+0xc(%a6) # Save incr value
4717 mov.l %d0,%d1
4718 add.l %a0,%d1 # Increment
4719 mov.l %d1,%a2 # Save incr value
4725 mov.l %d0,%d1
4726 add.l %a0,%d1 # Increment
4727 mov.l %d1,%a3 # Save incr value
4733 mov.l %d0,%d1
4734 add.l %a0,%d1 # Increment
4735 mov.l %d1,%a4 # Save incr value
4741 mov.l %d0,%d1
4742 add.l %a0,%d1 # Increment
4743 mov.l %d1,%a5 # Save incr value
4749 mov.l %d0,%d1
4750 add.l %a0,%d1 # Increment
4751 mov.l %d1,(%a6) # Save incr value
4759 mov.l %d0,%d1
4760 add.l %a0,%d1 # Increment
4761 mov.l %d1,EXC_A7(%a6) # Save incr value
4834 tst.l %d1 # did ifetch fail?
4847 tst.l %d1 # did ifetch fail?
4860 tst.l %d1 # did ifetch fail?
4873 tst.l %d1 # did ifetch fail?
4886 tst.l %d1 # did ifetch fail?
4899 tst.l %d1 # did ifetch fail?
4912 tst.l %d1 # did ifetch fail?
4925 tst.l %d1 # did ifetch fail?
4940 addq.l &0x8,%d1
4948 tst.l %d1 # did ifetch fail?
4958 mov.l %d0,%d1
4959 rol.w &0x4,%d1
4960 andi.w &0xf,%d1 # extract index regno
4972 mov.l %d2,%d1
4973 rol.w &0x7,%d1
4974 andi.l &0x3,%d1 # extract scale value
4976 lsl.l %d1,%d0 # shift index by scale
4993 tst.l %d1 # did ifetch fail?
5007 tst.l %d1 # did ifetch fail?
5021 tst.l %d1 # did ifetch fail?
5043 tst.l %d1 # did ifetch fail?
5054 mov.l %d0,%d1 # make extword copy
5055 rol.w &0x4,%d1 # rotate reg num into place
5056 andi.w &0xf,%d1 # extract register number
5068 mov.l %d2,%d1
5069 rol.w &0x7,%d1 # rotate scale value into place
5070 andi.l &0x3,%d1 # extract scale value
5072 lsl.l %d1,%d0 # shift index by scale
5100 bfextu %d0{&16:&4},%d1 # fetch dreg index
5136 tst.l %d1 # did ifetch fail?
5146 tst.l %d1 # did ifetch fail?
5167 tst.l %d1 # did ifetch fail?
5177 tst.l %d1 # did ifetch fail?
5195 tst.l %d1 # did dfetch fail?
5207 tst.l %d1 # did dfetch fail?
5300 tst.l %d1 # did ifetch fail?
5308 tst.l %d1 # did ifetch fail?
5320 tst.l %d1 # did ifetch fail?
5328 tst.l %d1 # did ifetch fail?
5340 tst.l %d1 # did ifetch fail?
5348 tst.l %d1 # did ifetch fail?
5360 tst.l %d1 # did ifetch fail?
5368 tst.l %d1 # did ifetch fail?
5376 tst.l %d1 # did ifetch fail?
5419 mov.w DST_EX(%a1),%d1
5421 mov.w %d1,FP_SCR1_EX(%a6)
5424 andi.w &0x7fff,%d1
5426 mov.w %d1,2+L_SCR1(%a6) # store dst exponent
5428 cmp.w %d0, %d1 # is src exp >= dst exp?
5453 mov.w FP_SCR0_EX(%a6),%d1
5454 and.w &0x8000,%d1
5455 or.w %d1,%d0 # concat {sgn,new exp}
5489 mov.w FP_SCR1_EX(%a6),%d1
5490 andi.w &0x8000,%d1
5491 or.w %d1,%d0 # concat {sgn,new exp}
5531 mov.w FP_SCR0_EX(%a6),%d1 # extract operand's {sgn,exp}
5532 mov.w %d1,%d0 # make a copy
5534 andi.l &0x7fff,%d1 # extract operand's exponent
5546 sub.l %d1,%d0 # scale = BIAS + (-exp)
5554 mov.l %d0,%d1 # prepare for op_norm call
5588 mov.w FP_SCR0_EX(%a6),%d1 # extract operand's {sgn,exp}
5589 andi.l &0x7fff,%d1 # extract operand's exponent
5593 btst &0x0,%d1 # is exp even or odd?
5599 sub.l %d1,%d0 # scale = BIAS + (-exp)
5607 sub.l %d1,%d0 # scale = BIAS + (-exp)
5658 mov.w FP_SCR1_EX(%a6),%d1 # extract operand's {sgn,exp}
5659 mov.w %d1,%d0 # make a copy
5661 andi.l &0x7fff,%d1 # extract operand's exponent
5673 sub.l %d1,%d0 # scale = BIAS + (-exp)
5680 mov.l %d0,%d1 # prepare for op_norm call
5841 mov.w (tbl_thresh.b,%pc,%d0.w*2), %d1 # load prec threshold
5842 mov.w %d1, %d0 # copy d1 into d0
5862 mov.w %d1, FTEMP_EX(%a0) # load exp with threshold
5863 clr.l FTEMP_HI(%a0) # set d1 = 0 (ms mantissa)
5873 # %d1{15:0} : denormalization threshold #
5897 mov.l %d1, %d0 # copy the denorm threshold
5898 sub.w FTEMP_EX(%a0), %d1 # d1 = threshold - uns exponent
5899 ble.b dnrm_no_lp # d1 <= 0
5900 cmpi.w %d1, &0x20 # is ( 0 <= d1 < 32) ?
5902 cmpi.w %d1, &0x40 # is (32 <= d1 < 64) ?
5904 bra.w case_3 # (d1 >= 64)
5914 # case (0<d1<32)
5917 # %d1 = "n" = amt to shift
5941 sub.w %d1, %d0 # %d0 = 32 - %d1
5943 cmpi.w %d1, &29 # is shft amt >= 29
5950 bfextu FTEMP_HI(%a0){%d0:&32}, %d1 # %d1 = new FTEMP_LO
5954 mov.l %d1, FTEMP_LO(%a0) # store new FTEMP_LO
5966 # case (32<=d1<64)
5969 # %d1 = "n" = amt to shift
5992 subi.w &0x20, %d1 # %d1 now between 0 and 32
5994 sub.w %d1, %d0 # %d0 = 32 - %d1
6003 bfextu FTEMP_HI(%a0){%d0:&32}, %d1 # %d1 = new G,R,S
6005 bftst %d1{&2:&30} # were any bits shifted off?
6010 mov.l %d1, %d0 # move new G,R,S to %d0
6014 mov.l %d1, %d0 # move new G,R,S to %d0
6026 # case (d1>=64)
6029 # %d1 = amt to shift
6034 cmpi.w %d1, &65 # is shift amt > 65?
6039 # case (d1>65)
6050 # case (d1 == 64)
6071 mov.l %d0, %d1 # make a copy
6073 and.l &0x3fffffff, %d1 # extract other bits
6078 # case (d1 == 65)
6101 and.l &0x7fffffff, %d1 # extract other bits
6140 # d1(hi) = contains rounding precision: #
6144 # d1(lo) = contains rounding mode: #
6184 mov.w (tbl_mode.b,%pc,%d1.w*2), %a1 # load jump offset
6203 swap %d1 # set up d1 for round prec.
6205 cmpi.b %d1, &s_mode # is prec = sgl?
6220 swap %d1 # set up d1 for round prec.
6222 cmpi.b %d1, &s_mode # is prec = sgl?
6237 swap %d1 # set up d1 for round prec.
6239 cmpi.b %d1, &s_mode # is prec = sgl?
6313 swap %d1 # select rnd prec
6315 cmpi.b %d1, &s_mode # is prec sgl?
6327 # d1 = {PREC,ROUND}
6336 # Notes: the ext_grs uses the round PREC, and therefore has to swap d1
6337 # prior to usage, and needs to restore d1 to original. this
6343 swap %d1 # have d1.w point to round precision
6344 tst.b %d1 # is rnd prec = extended?
6352 swap %d1 # yes; return to correct positions
6358 cmpi.b %d1, &s_mode # is rnd prec = sgl?
6416 swap %d1 # restore d1 to original
6444 mov.l FTEMP_LO(%a0), %d1 # load lo(mantissa)
6451 bfextu %d1{&0:%d2}, %d3 # extract lo bits
6454 lsl.l %d2, %d1 # create lo(man)
6457 mov.l %d1, FTEMP_LO(%a0) # store new lo(man)
6467 bfffo %d1{&0:&32}, %d2 # how many places to shift?
6468 lsl.l %d2, %d1 # shift lo(man)
6471 mov.l %d1, FTEMP_HI(%a0) # store hi(man)
6519 clr.l %d1 # clear top word
6520 mov.w FTEMP_EX(%a0), %d1 # extract exponent
6521 and.w &0x7fff, %d1 # strip off sgn
6523 cmp.w %d0, %d1 # will denorm push exp < 0?
6529 sub.w %d0, %d1 # shift exponent value
6532 or.w %d0, %d1 # {sgn,new exp}
6533 mov.w %d1, FTEMP_EX(%a0) # insert new exponent
6544 cmp.b %d1, &32 # is exp <= 32?
6547 bfextu FTEMP_HI(%a0){%d1:&32}, %d0 # extract new hi(man)
6551 lsl.l %d1, %d0 # extract new lo(man)
6563 sub.w &32, %d1 # adjust shft amt by 32
6566 lsl.l %d1, %d0 # left shift lo(man)
6688 mov.l %d0, %d1
6700 and.l &0x000fffff, %d1
6711 and.l &0x000fffff, %d1
6719 btst &19, %d1
6751 mov.l %d0, %d1
6763 and.l &0x007fffff, %d1
6772 and.l &0x007fffff, %d1
6778 btst &22, %d1
6802 # d1 = rounding precision/mode #
6823 mov.l %d1, -(%sp) # save rnd prec,mode on stack
6828 mov.w FTEMP_EX(%a0), %d1 # extract exponent
6829 and.w &0x7fff, %d1
6830 sub.w %d0, %d1
6831 mov.w %d1, FTEMP_EX(%a0) # insert 16 bit exponent
6841 mov.w 0x6(%sp),%d1 # load prec:mode into %d1
6842 andi.w &0xc0,%d1 # extract rnd prec
6843 lsr.w &0x4,%d1
6844 swap %d1
6845 mov.w 0x6(%sp),%d1
6846 andi.w &0x30,%d1
6847 lsr.w &0x4,%d1
6887 mov.l %d1,-(%sp) # save rnd prec,mode on stack
6892 mov.w FTEMP_EX(%a0),%d1 # extract exponent
6893 and.w &0x7fff,%d1
6894 sub.w %d0,%d1
6895 mov.w %d1,FTEMP_EX(%a0) # insert 16 bit exponent
6903 mov.w &s_mode,%d1 # force rnd prec = sgl
6904 swap %d1
6905 mov.w 0x6(%sp),%d1 # load rnd mode
6906 andi.w &0x30,%d1 # extract rnd prec
6907 lsr.w &0x4,%d1
6955 # d1.b = '-1' => (-); '0' => (+) #
6978 andi.w &0x10,%d1 # keep result sign
6980 or.b %d0,%d1 # concat the two
6981 mov.w %d1,%d0 # make a copy
6982 lsl.b &0x1,%d1 # multiply d1 by 2
6987 and.w &0x10, %d1 # keep result sign
6988 or.b %d0, %d1 # insert rnd mode
6990 or.b %d0, %d1 # insert rnd prec
6991 mov.w %d1, %d0 # make a copy
6992 lsl.b &0x1, %d1 # shift left by 1
7000 lea (tbl_ovfl_result.b,%pc,%d1.w*8), %a0 # return result ptr
7102 bfextu EXC_CMDREG(%a6){&3:&3},%d1 # extract dst fmt
7103 mov.w (tbl_fout.b,%pc,%d1.w*2),%a1 # use as index
7135 fmov.l %fpsr,%d1 # fetch FPSR
7136 or.w %d1,2+USER_FPSR(%a6) # save new exc,accrued bits
7138 mov.b 1+EXC_OPWORD(%a6),%d1 # extract dst mode
7139 andi.b &0x38,%d1 # is mode == 0? (Dreg dst)
7145 tst.l %d1 # did dstore fail?
7151 mov.b 1+EXC_OPWORD(%a6),%d1 # extract Dn
7152 andi.w &0x7,%d1
7157 mov.l SRC_EX(%a0),%d1
7158 andi.l &0x80000000,%d1 # keep DENORM sign
7159 ori.l &0x00800000,%d1 # make smallest sgl
7160 fmov.s %d1,%fp0
7181 fmov.l %fpsr,%d1 # fetch FPSR
7182 or.w %d1,2+USER_FPSR(%a6) # save new exc,accrued bits
7184 mov.b 1+EXC_OPWORD(%a6),%d1 # extract dst mode
7185 andi.b &0x38,%d1 # is mode == 0? (Dreg dst)
7191 tst.l %d1 # did dstore fail?
7197 mov.b 1+EXC_OPWORD(%a6),%d1 # extract Dn
7198 andi.w &0x7,%d1
7203 mov.l SRC_EX(%a0),%d1
7204 andi.l &0x80000000,%d1 # keep DENORM sign
7205 ori.l &0x00800000,%d1 # make smallest sgl
7206 fmov.s %d1,%fp0
7227 fmov.l %fpsr,%d1 # fetch FPSR
7228 or.w %d1,2+USER_FPSR(%a6) # save new exc,accrued bits
7231 mov.b 1+EXC_OPWORD(%a6),%d1 # extract dst mode
7232 andi.b &0x38,%d1 # is mode == 0? (Dreg dst)
7238 tst.l %d1 # did dstore fail?
7244 mov.b 1+EXC_OPWORD(%a6),%d1 # extract Dn
7245 andi.w &0x7,%d1
7250 mov.l SRC_EX(%a0),%d1
7251 andi.l &0x80000000,%d1 # keep DENORM sign
7252 ori.l &0x00800000,%d1 # make smallest sgl
7253 fmov.s %d1,%fp0
7289 tst.l %d1 # did dstore fail?
7310 tst.l %d1 # did dstore fail?
7367 fmov.l %fpsr,%d1 # save FPSR
7369 or.w %d1,2+USER_FPSR(%a6) # set possible inex2/ainex
7372 mov.b 1+EXC_OPWORD(%a6),%d1 # extract dst mode
7373 andi.b &0x38,%d1 # is mode == 0? (Dreg dst)
7379 tst.l %d1 # did dstore fail?
7385 mov.b 1+EXC_OPWORD(%a6),%d1 # extract Dn
7386 andi.w &0x7,%d1
7413 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode
7419 mov.b 1+EXC_OPWORD(%a6),%d1 # extract dst mode
7420 andi.b &0x38,%d1 # is mode == 0? (Dreg dst)
7426 tst.l %d1 # did dstore fail?
7432 mov.b 1+EXC_OPWORD(%a6),%d1 # extract Dn
7433 andi.w &0x7,%d1
7437 mov.b FPCR_ENABLE(%a6),%d1
7438 andi.b &0x0a,%d1 # is UNFL or INEX enabled?
7463 smi %d1 # set if so
7469 mov.b 1+EXC_OPWORD(%a6),%d1 # extract dst mode
7470 andi.b &0x38,%d1 # is mode == 0? (Dreg dst)
7476 tst.l %d1 # did dstore fail?
7482 mov.b 1+EXC_OPWORD(%a6),%d1 # extract Dn
7483 andi.w &0x7,%d1
7487 mov.b FPCR_ENABLE(%a6),%d1
7488 andi.b &0x0a,%d1 # is UNFL or INEX enabled?
7502 mov.w SRC_EX(%a0),%d1 # fetch current sign
7503 andi.w &0x8000,%d1 # keep it,clear exp
7504 ori.w &0x3fff,%d1 # insert exp = 0
7505 mov.w %d1,FP_SCR0_EX(%a6) # insert scaled exp
7551 mov.b 3+L_SCR3(%a6),%d1
7552 lsr.b &0x4,%d1
7553 andi.w &0x0c,%d1
7554 swap %d1
7555 mov.b 3+L_SCR3(%a6),%d1
7556 lsr.b &0x4,%d1
7557 andi.w &0x03,%d1
7614 tst.l %d1 # did dstore fail?
7642 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode
7648 mov.l %d1,L_SCR2(%a6)
7655 tst.l %d1 # did dstore fail?
7658 mov.b FPCR_ENABLE(%a6),%d1
7659 andi.b &0x0a,%d1 # is UNFL or INEX enabled?
7684 smi %d1 # set if so
7695 tst.l %d1 # did dstore fail?
7698 mov.b FPCR_ENABLE(%a6),%d1
7699 andi.b &0x0a,%d1 # is UNFL or INEX enabled?
7713 mov.w SRC_EX(%a0),%d1 # fetch current sign
7714 andi.w &0x8000,%d1 # keep it,clear exp
7715 ori.w &0x3fff,%d1 # insert exp = 0
7716 mov.w %d1,FP_SCR0_EX(%a6) # insert scaled exp
7742 # d1 = lo(double precision result) #
7783 mov.l FTEMP_HI(%a0),%d1 # get ms mantissa
7784 bfextu %d1{&1:&20},%d1 # get upper 20 bits of ms
7785 or.l %d1,%d0 # put these bits in ms word of double
7787 mov.l FTEMP_HI(%a0),%d1 # get ms mantissa
7789 lsl.l %d0,%d1 # put lower 11 bits in upper bits
7790 mov.l %d1,L_SCR2(%a6) # build lower lword in memory
7791 mov.l FTEMP_LO(%a0),%d1 # get ls mantissa
7792 bfextu %d1{&0:&21},%d0 # get ls 21 bits of double
7793 mov.l L_SCR2(%a6),%d1
7794 or.l %d0,%d1 # put them in double result
7848 mov.l FTEMP_HI(%a0),%d1 # get ms mantissa
7849 andi.l &0x7fffff00,%d1 # get upper 23 bits of ms
7850 lsr.l &0x8,%d1 # and put them flush right
7851 or.l %d1,%d0 # put these bits in ms word of single
7867 mov.b 1+EXC_CMDREG(%a6),%d1 # fetch dynamic reg
7868 lsr.b &0x4,%d1
7869 andi.w &0x7,%d1
7923 tst.l %d1 # did dstore fail?
7933 tst.l %d1 # did dstore fail?
8012 clr.w %d1
8013 mov.b DTAG(%a6),%d1
8014 lsl.b &0x3,%d1
8015 or.b STAG(%a6),%d1 # combine src tags
8034 mov.w 2+L_SCR3(%a6),%d1 # fetch precision
8035 lsr.b &0x6,%d1 # shift to lo bits
8037 cmp.l %d0,(tbl_fmul_ovfl.w,%pc,%d1.w*4) # would result ovfl?
8041 cmp.l %d0,(tbl_fmul_unfl.w,%pc,%d1.w*4) # would result unfl?
8061 fmov.l %fpsr,%d1 # save status
8064 or.l %d1,USER_FPSR(%a6) # save INEX2,N
8069 mov.w FP_SCR0_EX(%a6),%d1 # load {sgn,exp}
8070 mov.l %d1,%d2 # make a copy
8071 andi.l &0x7fff,%d1 # strip sign
8073 sub.l %d0,%d1 # add scale factor
8074 or.w %d2,%d1 # concat old sign,new exp
8075 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
8101 fmov.l %fpsr,%d1 # save status
8104 or.l %d1,USER_FPSR(%a6) # save INEX2,N
8110 mov.b FPCR_ENABLE(%a6),%d1
8111 andi.b &0x13,%d1 # is OVFL or INEX enabled?
8117 sne %d1 # set sign param accordingly
8131 mov.l L_SCR3(%a6),%d1
8132 andi.b &0xc0,%d1 # test the rnd prec
8139 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
8140 mov.w %d1,%d2 # make a copy
8141 andi.l &0x7fff,%d1 # strip sign
8142 sub.l %d0,%d1 # add scale factor
8143 subi.l &0x6000,%d1 # subtract bias
8144 andi.w &0x7fff,%d1 # clear sign bit
8146 or.w %d2,%d1 # concat old sign,new exp
8147 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
8155 mov.l L_SCR3(%a6),%d1
8156 andi.b &0x30,%d1 # keep rnd mode only
8157 fmov.l %d1,%fpcr # set FPCR
8179 fmov.l %fpsr,%d1 # save status
8182 or.l %d1,USER_FPSR(%a6) # save INEX2,N
8217 fmov.l %fpsr,%d1 # save status
8220 or.l %d1,USER_FPSR(%a6) # save INEX2,N
8222 mov.b FPCR_ENABLE(%a6),%d1
8223 andi.b &0x0b,%d1 # is UNFL or INEX enabled?
8230 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode
8242 mov.l L_SCR3(%a6),%d1
8243 andi.b &0xc0,%d1 # is precision extended?
8259 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
8260 mov.l %d1,%d2 # make a copy
8261 andi.l &0x7fff,%d1 # strip sign
8263 sub.l %d0,%d1 # add scale factor
8264 addi.l &0x6000,%d1 # add bias
8265 andi.w &0x7fff,%d1
8266 or.w %d2,%d1 # concat old sign,new exp
8267 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
8273 mov.l L_SCR3(%a6),%d1
8274 andi.b &0x30,%d1 # use only rnd mode
8275 fmov.l %d1,%fpcr # set FPCR
8290 fmov.l %fpsr,%d1 # save status
8293 or.l %d1,USER_FPSR(%a6) # save INEX2,N
8309 mov.l L_SCR3(%a6),%d1
8310 andi.b &0xc0,%d1 # keep rnd prec
8311 ori.b &rz_mode*0x10,%d1 # insert RZ
8313 fmov.l %d1,%fpcr # set FPCR
8330 mov.w (tbl_fmul_op.b,%pc,%d1.w*2),%d1
8331 jmp (tbl_fmul_op.b,%pc,%d1.w)
8402 mov.b DST_EX(%a1),%d1
8403 eor.b %d0,%d1
8426 mov.b DST_EX(%a1),%d1
8427 eor.b %d0,%d1
8443 mov.b DST_EX(%a1),%d1
8444 eor.b %d0,%d1
8497 mov.b STAG(%a6),%d1 # fetch src optype tag
8550 mov.w FP_SCR0_EX(%a6),%d1 # fetch old sign,exp
8551 andi.w &0x8000,%d1 # keep old sign
8553 or.w %d1,%d0 # concat new exo,old sign
8589 fmov.l %fpsr,%d1 # save FPSR
8592 or.l %d1,USER_FPSR(%a6) # save INEX2,N
8597 mov.w FP_SCR0_EX(%a6),%d1 # load {sgn,exp}
8598 mov.w %d1,%d2 # make a copy
8599 andi.l &0x7fff,%d1 # strip sign
8600 sub.l %d0,%d1 # add scale factor
8602 or.w %d1,%d2 # concat old sign,new exponent
8636 mov.b FPCR_ENABLE(%a6),%d1
8637 andi.b &0x0b,%d1 # is UNFL or INEX enabled?
8642 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode
8655 mov.w FP_SCR0_EX(%a6),%d1 # load current exponent
8658 mov.w %d1,%d2 # make a copy
8659 andi.l &0x7fff,%d1 # strip sign
8660 sub.l %d0,%d1 # subtract scale factor
8662 addi.l &0x6000,%d1 # add new bias
8663 andi.w &0x7fff,%d1
8664 or.w %d1,%d2 # concat old sign,new exp
8680 fmov.l %fpsr,%d1 # save FPSR
8682 or.l %d1,USER_FPSR(%a6) # save INEX2,N
8687 mov.b FPCR_ENABLE(%a6),%d1
8688 andi.b &0x13,%d1 # is OVFL or INEX enabled?
8697 sne %d1 # set sign param accordingly
8711 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
8712 mov.l %d1,%d2 # make a copy
8713 andi.l &0x7fff,%d1 # strip sign
8715 sub.l %d0,%d1 # add scale factor
8716 sub.l &0x6000,%d1 # subtract bias
8717 andi.w &0x7fff,%d1
8718 or.w %d2,%d1
8719 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
8733 fmov.l %fpsr,%d1 # save status
8736 or.l %d1,USER_FPSR(%a6) # save INEX2,N
8751 cmpi.b %d1,&DENORM # weed out DENORM
8753 cmpi.b %d1,&SNAN # weed out SNANs
8755 cmpi.b %d1,&QNAN # weed out QNANs
8830 clr.w %d1
8831 mov.b DTAG(%a6),%d1
8832 lsl.b &0x3,%d1
8833 or.b STAG(%a6),%d1 # combine src tags
8857 mov.w 2+L_SCR3(%a6),%d1 # fetch precision
8858 lsr.b &0x6,%d1 # shift to lo bits
8860 cmp.l %d0,(tbl_fdiv_ovfl.b,%pc,%d1.w*4) # will result overflow?
8863 cmp.l %d0,(tbl_fdiv_unfl.w,%pc,%d1.w*4) # will result underflow?
8875 fmov.l %fpsr,%d1 # save FPSR
8878 or.l %d1,USER_FPSR(%a6) # save INEX2,N
8883 mov.w FP_SCR0_EX(%a6),%d1 # load {sgn,exp}
8884 mov.l %d1,%d2 # make a copy
8885 andi.l &0x7fff,%d1 # strip sign
8887 sub.l %d0,%d1 # add scale factor
8888 or.w %d2,%d1 # concat old sign,new exp
8889 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
8923 cmp.l %d0,(tbl_fdiv_ovfl2.b,%pc,%d1.w*4)
8930 mov.b FPCR_ENABLE(%a6),%d1
8931 andi.b &0x13,%d1 # is OVFL or INEX enabled?
8936 sne %d1 # set sign param accordingly
8944 mov.l L_SCR3(%a6),%d1
8945 andi.b &0xc0,%d1 # is precision extended?
8952 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
8953 mov.w %d1,%d2 # make a copy
8954 andi.l &0x7fff,%d1 # strip sign
8955 sub.l %d0,%d1 # add scale factor
8956 subi.l &0x6000,%d1 # subtract bias
8957 andi.w &0x7fff,%d1 # clear sign bit
8959 or.w %d2,%d1 # concat old sign,new exp
8960 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
8968 mov.l L_SCR3(%a6),%d1
8969 andi.b &0x30,%d1 # keep rnd mode
8970 fmov.l %d1,%fpcr # set FPCR
8987 fmov.l %fpsr,%d1 # save status
8990 or.l %d1,USER_FPSR(%a6) # save INEX2,N
8992 mov.b FPCR_ENABLE(%a6),%d1
8993 andi.b &0x0b,%d1 # is UNFL or INEX enabled?
9000 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode
9012 mov.l L_SCR3(%a6),%d1
9013 andi.b &0xc0,%d1 # is precision extended?
9027 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
9028 mov.l %d1,%d2 # make a copy
9029 andi.l &0x7fff,%d1 # strip sign
9031 sub.l %d0,%d1 # add scale factoer
9032 addi.l &0x6000,%d1 # add bias
9033 andi.w &0x7fff,%d1
9034 or.w %d2,%d1 # concat old sign,new exp
9035 mov.w %d1,FP_SCR0_EX(%a6) # insert new exp
9041 mov.l L_SCR3(%a6),%d1
9042 andi.b &0x30,%d1 # use only rnd mode
9043 fmov.l %d1,%fpcr # set FPCR
9058 fmov.l %fpsr,%d1 # save status
9061 or.l %d1,USER_FPSR(%a6) # save INEX2,N
9077 mov.l L_SCR3(%a6),%d1
9078 andi.b &0xc0,%d1 # keep rnd prec
9079 ori.b &rz_mode*0x10,%d1 # insert RZ
9081 fmov.l %d1,%fpcr # set FPCR
9098 mov.w (tbl_fdiv_op.b,%pc,%d1.w*2),%d1
9099 jmp (tbl_fdiv_op.b,%pc,%d1.w*1)
9167 mov.b DST_EX(%a1),%d1 # or of input signs.
9168 eor.b %d0,%d1
9187 mov.b DST_EX(%a1),%d1
9188 eor.b %d0,%d1
9207 mov.b SRC_EX(%a0),%d1
9208 eor.b %d0,%d1
9270 mov.b STAG(%a6),%d1
9330 mov.w FP_SCR0_EX(%a6),%d1 # fetch old sign,exp
9331 andi.w &0x8000,%d1 # keep old sign
9333 or.w %d1,%d0 # concat old sign, new exponent
9369 fmov.l %fpsr,%d1 # save FPSR
9372 or.l %d1,USER_FPSR(%a6) # save INEX2,N
9377 mov.w FP_SCR0_EX(%a6),%d1 # load sgn,exp
9378 mov.w %d1,%d2 # make a copy
9379 andi.l &0x7fff,%d1 # strip sign
9380 sub.l %d0,%d1 # add scale factor
9382 or.w %d1,%d2 # concat old sign,new exp
9416 mov.b FPCR_ENABLE(%a6),%d1
9417 andi.b &0x0b,%d1 # is UNFL or INEX enabled?
9422 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode
9435 mov.w FP_SCR0_EX(%a6),%d1 # load current exponent
9438 mov.l %d1,%d2 # make a copy
9439 andi.l &0x7fff,%d1 # strip sign
9441 sub.l %d0,%d1 # subtract scale factor
9442 addi.l &0x6000,%d1 # add new bias
9443 andi.w &0x7fff,%d1
9444 or.w %d2,%d1 # concat new sign,new exp
9445 mov.w %d1,FP_SCR1_EX(%a6) # insert new exp
9460 fmov.l %fpsr,%d1 # save FPSR
9462 or.l %d1,USER_FPSR(%a6) # save INEX2,N
9467 mov.b FPCR_ENABLE(%a6),%d1
9468 andi.b &0x13,%d1 # is OVFL or INEX enabled?
9477 sne %d1 # set sign param accordingly
9491 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
9492 mov.l %d1,%d2 # make a copy
9493 andi.l &0x7fff,%d1 # strip sign
9495 sub.l %d0,%d1 # add scale factor
9496 subi.l &0x6000,%d1 # subtract bias
9497 andi.w &0x7fff,%d1
9498 or.w %d2,%d1 # concat sign,exp
9499 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
9513 fmov.l %fpsr,%d1 # save status
9516 or.l %d1,USER_FPSR(%a6) # save INEX2,N
9531 cmpi.b %d1,&DENORM # weed out DENORM
9533 cmpi.b %d1,&SNAN # weed out SNAN
9535 cmpi.b %d1,&QNAN # weed out QNAN
9570 mov.b STAG(%a6),%d1
9588 cmpi.b %d1,&ZERO # weed out ZERO
9590 cmpi.b %d1,&INF # weed out INF
9592 cmpi.b %d1,&SNAN # weed out SNAN
9594 cmpi.b %d1,&QNAN # weed out QNAN
9662 mov.b STAG(%a6),%d1
9686 cmpi.b %d1,&ZERO # weed out ZERO
9688 cmpi.b %d1,&INF # weed out INF
9690 cmpi.b %d1,&DENORM # weed out DENORM
9692 cmpi.b %d1,&SNAN # weed out SNAN
9768 mov.b STAG(%a6),%d1
9788 cmpi.b %d1,&ZERO # weed out ZERO
9790 cmpi.b %d1,&INF # weed out INF
9792 cmpi.b %d1,&DENORM # weed out DENORM
9794 cmpi.b %d1,&SNAN # weed out SNAN
9893 mov.b STAG(%a6),%d1
9910 mov.w SRC_EX(%a0),%d1
9911 bclr &15,%d1 # force absolute value
9912 mov.w %d1,FP_SCR0_EX(%a6) # insert exponent
9948 mov.w FP_SCR0_EX(%a6),%d1 # fetch old sign,exp
9949 andi.w &0x8000,%d1 # keep old sign
9951 or.w %d1,%d0 # concat old sign, new exponent
9987 fmov.l %fpsr,%d1 # save FPSR
9990 or.l %d1,USER_FPSR(%a6) # save INEX2,N
9995 mov.w FP_SCR0_EX(%a6),%d1 # load sgn,exp
9996 mov.l %d1,%d2 # make a copy
9997 andi.l &0x7fff,%d1 # strip sign
9998 sub.l %d0,%d1 # add scale factor
10000 or.w %d1,%d2 # concat old sign,new exp
10031 mov.b FPCR_ENABLE(%a6),%d1
10032 andi.b &0x0b,%d1 # is UNFL or INEX enabled?
10037 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode
10050 mov.w FP_SCR0_EX(%a6),%d1 # load current exponent
10053 mov.l %d1,%d2 # make a copy
10054 andi.l &0x7fff,%d1 # strip sign
10056 sub.l %d0,%d1 # subtract scale factor
10057 addi.l &0x6000,%d1 # add new bias
10058 andi.w &0x7fff,%d1
10059 or.w %d2,%d1 # concat new sign,new exp
10060 mov.w %d1,FP_SCR1_EX(%a6) # insert new exp
10075 fmov.l %fpsr,%d1 # save FPSR
10077 or.l %d1,USER_FPSR(%a6) # save INEX2,N
10082 mov.b FPCR_ENABLE(%a6),%d1
10083 andi.b &0x13,%d1 # is OVFL or INEX enabled?
10092 sne %d1 # set sign param accordingly
10106 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
10107 mov.l %d1,%d2 # make a copy
10108 andi.l &0x7fff,%d1 # strip sign
10110 sub.l %d0,%d1 # add scale factor
10111 subi.l &0x6000,%d1 # subtract bias
10112 andi.w &0x7fff,%d1
10113 or.w %d2,%d1 # concat sign,exp
10114 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
10128 fmov.l %fpsr,%d1 # save status
10131 or.l %d1,USER_FPSR(%a6) # save INEX2,N
10146 cmpi.b %d1,&DENORM # weed out DENORM
10148 cmpi.b %d1,&SNAN # weed out SNAN
10150 cmpi.b %d1,&QNAN # weed out QNAN
10155 cmpi.b %d1,&INF # weed out INF
10189 clr.w %d1
10190 mov.b DTAG(%a6),%d1
10191 lsl.b &0x3,%d1
10192 or.b STAG(%a6),%d1
10213 mov.w (tbl_fcmp_op.b,%pc,%d1.w*2),%d1
10214 jmp (tbl_fcmp_op.b,%pc,%d1.w*1)
10330 mov.b DST_EX(%a1),%d1
10331 eor.b %d0,%d1
10344 mov.b DST_EX(%a1),%d1
10345 eor.b %d0,%d1
10393 clr.w %d1
10394 mov.b DTAG(%a6),%d1
10395 lsl.b &0x3,%d1
10396 or.b STAG(%a6),%d1
10432 fmov.l %fpsr,%d1 # save status
10435 or.l %d1,USER_FPSR(%a6) # save INEX2,N
10440 mov.w FP_SCR0_EX(%a6),%d1 # load {sgn,exp}
10441 mov.l %d1,%d2 # make a copy
10442 andi.l &0x7fff,%d1 # strip sign
10444 sub.l %d0,%d1 # add scale factor
10445 or.w %d2,%d1 # concat old sign,new exp
10446 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
10459 fmov.l %fpsr,%d1 # save status
10462 or.l %d1,USER_FPSR(%a6) # save INEX2,N
10469 mov.b FPCR_ENABLE(%a6),%d1
10470 andi.b &0x13,%d1 # is OVFL or INEX enabled?
10475 sne %d1 # set sign param accordingly
10487 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
10488 mov.l %d1,%d2 # make a copy
10489 andi.l &0x7fff,%d1 # strip sign
10490 sub.l %d0,%d1 # add scale factor
10491 subi.l &0x6000,%d1 # subtract bias
10492 andi.w &0x7fff,%d1
10494 or.w %d2,%d1 # concat old sign,new exp
10495 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
10508 fmov.l %fpsr,%d1 # save status
10511 or.l %d1,USER_FPSR(%a6) # save INEX2,N
10530 fmov.l %fpsr,%d1 # save status
10533 or.l %d1,USER_FPSR(%a6) # save INEX2,N
10535 mov.b FPCR_ENABLE(%a6),%d1
10536 andi.b &0x0b,%d1 # is UNFL or INEX enabled?
10543 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode
10564 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
10565 mov.l %d1,%d2 # make a copy
10566 andi.l &0x7fff,%d1 # strip sign
10568 sub.l %d0,%d1 # add scale factor
10569 addi.l &0x6000,%d1 # add bias
10570 andi.w &0x7fff,%d1
10571 or.w %d2,%d1 # concat old sign,new exp
10572 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
10585 fmov.l %fpsr,%d1 # save status
10588 or.l %d1,USER_FPSR(%a6) # save INEX2,N
10604 mov.l L_SCR3(%a6),%d1
10605 andi.b &0xc0,%d1 # keep rnd prec
10606 ori.b &rz_mode*0x10,%d1 # insert RZ
10608 fmov.l %d1,%fpcr # set FPCR
10625 mov.w (tbl_fsglmul_op.b,%pc,%d1.w*2),%d1
10626 jmp (tbl_fsglmul_op.b,%pc,%d1.w*1)
10734 clr.w %d1
10735 mov.b DTAG(%a6),%d1
10736 lsl.b &0x3,%d1
10737 or.b STAG(%a6),%d1 # combine src tags
10761 mov.w 2+L_SCR3(%a6),%d1 # fetch precision,mode
10762 lsr.b &0x6,%d1
10779 fmov.l %fpsr,%d1 # save FPSR
10782 or.l %d1,USER_FPSR(%a6) # save INEX2,N
10787 mov.w FP_SCR0_EX(%a6),%d1 # load {sgn,exp}
10788 mov.l %d1,%d2 # make a copy
10789 andi.l &0x7fff,%d1 # strip sign
10791 sub.l %d0,%d1 # add scale factor
10792 or.w %d2,%d1 # concat old sign,new exp
10793 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
10806 fmov.l %fpsr,%d1
10809 or.l %d1,USER_FPSR(%a6) # save INEX,N
10812 mov.w (%sp),%d1 # fetch new exponent
10814 andi.l &0x7fff,%d1 # strip sign
10815 sub.l %d0,%d1 # add scale factor
10816 cmp.l %d1,&0x7fff # did divide overflow?
10822 mov.b FPCR_ENABLE(%a6),%d1
10823 andi.b &0x13,%d1 # is OVFL or INEX enabled?
10828 sne %d1 # set sign param accordingly
10840 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
10841 mov.l %d1,%d2 # make a copy
10842 andi.l &0x7fff,%d1 # strip sign
10844 sub.l %d0,%d1 # add scale factor
10845 subi.l &0x6000,%d1 # subtract new bias
10846 andi.w &0x7fff,%d1 # clear ms bit
10847 or.w %d2,%d1 # concat old sign,new exp
10848 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
10863 fmov.l %fpsr,%d1 # save status
10866 or.l %d1,USER_FPSR(%a6) # save INEX2,N
10868 mov.b FPCR_ENABLE(%a6),%d1
10869 andi.b &0x0b,%d1 # is UNFL or INEX enabled?
10876 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode
10897 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
10898 mov.l %d1,%d2 # make a copy
10899 andi.l &0x7fff,%d1 # strip sign
10901 sub.l %d0,%d1 # add scale factor
10902 addi.l &0x6000,%d1 # add bias
10903 andi.w &0x7fff,%d1 # clear top bit
10904 or.w %d2,%d1 # concat old sign, new exp
10905 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
10921 fmov.l %fpsr,%d1 # save status
10924 or.l %d1,USER_FPSR(%a6) # save INEX2,N
10940 clr.l %d1 # clear scratch register
10941 ori.b &rz_mode*0x10,%d1 # force RZ rnd mode
10943 fmov.l %d1,%fpcr # set FPCR
10960 mov.w (tbl_fsgldiv_op.b,%pc,%d1.w*2),%d1
10961 jmp (tbl_fsgldiv_op.b,%pc,%d1.w*1)
11081 clr.w %d1
11082 mov.b DTAG(%a6),%d1
11083 lsl.b &0x3,%d1
11084 or.b STAG(%a6),%d1 # combine src tags
11103 fmov.l %fpsr,%d1 # fetch INEX2,N,Z
11105 or.l %d1,USER_FPSR(%a6) # save exc and ccode bits
11113 mov.w 2+L_SCR3(%a6),%d1
11114 lsr.b &0x6,%d1
11120 cmp.l %d2,(tbl_fadd_ovfl.b,%pc,%d1.w*4) # is it an overflow?
11123 cmp.l %d2,(tbl_fadd_unfl.b,%pc,%d1.w*4) # is it an underflow?
11128 mov.w (%sp),%d1
11129 andi.w &0x8000,%d1 # keep sign
11130 or.w %d2,%d1 # concat sign,new exp
11131 mov.w %d1,(%sp) # insert new exponent
11155 mov.b FPCR_ENABLE(%a6),%d1
11156 andi.b &0x13,%d1 # is OVFL or INEX enabled?
11162 sne %d1 # set sign param accordingly
11171 mov.b L_SCR3(%a6),%d1
11172 andi.b &0xc0,%d1 # is precision extended?
11176 mov.w (%sp),%d1
11177 andi.w &0x8000,%d1 # keep sign
11180 or.w %d2,%d1 # concat sign,new exp
11181 mov.w %d1,(%sp) # insert new exponent
11189 mov.l L_SCR3(%a6),%d1
11190 andi.b &0x30,%d1 # keep rnd mode
11191 fmov.l %d1,%fpcr # set FPCR
11214 fmov.l %fpsr,%d1 # save status
11216 or.l %d1,USER_FPSR(%a6) # save INEX,N
11218 mov.b FPCR_ENABLE(%a6),%d1
11219 andi.b &0x0b,%d1 # is UNFL or INEX enabled?
11226 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode
11236 mov.l L_SCR3(%a6),%d1
11237 andi.b &0xc0,%d1 # is precision extended?
11250 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
11251 mov.l %d1,%d2 # make a copy
11252 andi.l &0x7fff,%d1 # strip sign
11254 sub.l %d0,%d1 # add scale factor
11255 addi.l &0x6000,%d1 # add new bias
11256 andi.w &0x7fff,%d1 # clear top bit
11257 or.w %d2,%d1 # concat sign,new exp
11258 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
11263 mov.l L_SCR3(%a6),%d1
11264 andi.b &0x30,%d1 # use only rnd mode
11265 fmov.l %d1,%fpcr # set FPCR
11275 mov.l L_SCR3(%a6),%d1
11276 andi.b &0xc0,%d1
11279 mov.l 0x4(%sp),%d1 # extract hi(man)
11280 cmpi.l %d1,&0x80000000 # is hi(man) = 0x80000000?
11301 mov.l L_SCR3(%a6),%d1
11302 andi.b &0xc0,%d1 # keep rnd prec
11303 ori.b &rz_mode*0x10,%d1 # insert rnd mode
11304 fmov.l %d1,%fpcr # set FPCR
11324 mov.w (tbl_fadd_op.b,%pc,%d1.w*2),%d1
11325 jmp (tbl_fadd_op.b,%pc,%d1.w*1)
11393 mov.b DST_EX(%a1),%d1
11394 eor.b %d0,%d1
11411 mov.b 3+L_SCR3(%a6),%d1
11412 andi.b &0x30,%d1 # extract rnd mode
11413 cmpi.b %d1,&rm_mode*0x10 # is rnd mode == RM?
11454 mov.b DST_EX(%a1),%d1
11455 eor.b %d1,%d0
11534 clr.w %d1
11535 mov.b DTAG(%a6),%d1
11536 lsl.b &0x3,%d1
11537 or.b STAG(%a6),%d1 # combine src tags
11556 fmov.l %fpsr,%d1 # fetch INEX2, N, Z
11558 or.l %d1,USER_FPSR(%a6) # save exc and ccode bits
11566 mov.w 2+L_SCR3(%a6),%d1
11567 lsr.b &0x6,%d1
11573 cmp.l %d2,(tbl_fsub_ovfl.b,%pc,%d1.w*4) # is it an overflow?
11576 cmp.l %d2,(tbl_fsub_unfl.b,%pc,%d1.w*4) # is it an underflow?
11581 mov.w (%sp),%d1
11582 andi.w &0x8000,%d1 # keep sign
11583 or.w %d2,%d1 # insert new exponent
11584 mov.w %d1,(%sp) # insert new exponent
11608 mov.b FPCR_ENABLE(%a6),%d1
11609 andi.b &0x13,%d1 # is OVFL or INEX enabled?
11615 sne %d1 # set sign param accordingly
11624 mov.b L_SCR3(%a6),%d1
11625 andi.b &0xc0,%d1 # is precision extended?
11629 mov.w (%sp),%d1 # fetch {sgn,exp}
11630 andi.w &0x8000,%d1 # keep sign
11633 or.w %d2,%d1 # concat sign,exp
11634 mov.w %d1,(%sp) # insert new exponent
11642 mov.l L_SCR3(%a6),%d1
11643 andi.b &0x30,%d1 # clear rnd prec
11644 fmov.l %d1,%fpcr # set FPCR
11667 fmov.l %fpsr,%d1 # save status
11669 or.l %d1,USER_FPSR(%a6)
11671 mov.b FPCR_ENABLE(%a6),%d1
11672 andi.b &0x0b,%d1 # is UNFL or INEX enabled?
11679 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode
11689 mov.l L_SCR3(%a6),%d1
11690 andi.b &0xc0,%d1 # is precision extended?
11703 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
11704 mov.l %d1,%d2 # make a copy
11705 andi.l &0x7fff,%d1 # strip sign
11707 sub.l %d0,%d1 # add scale factor
11708 addi.l &0x6000,%d1 # subtract new bias
11709 andi.w &0x7fff,%d1 # clear top bit
11710 or.w %d2,%d1 # concat sgn,exp
11711 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
11716 mov.l L_SCR3(%a6),%d1
11717 andi.b &0x30,%d1 # clear rnd prec
11718 fmov.l %d1,%fpcr # set FPCR
11728 mov.l L_SCR3(%a6),%d1
11729 andi.b &0xc0,%d1 # fetch rnd prec
11732 mov.l 0x4(%sp),%d1
11733 cmpi.l %d1,&0x80000000 # is hi(man) = 0x80000000?
11754 mov.l L_SCR3(%a6),%d1
11755 andi.b &0xc0,%d1 # keep rnd prec
11756 ori.b &rz_mode*0x10,%d1 # insert rnd mode
11757 fmov.l %d1,%fpcr # set FPCR
11777 mov.w (tbl_fsub_op.b,%pc,%d1.w*2),%d1
11778 jmp (tbl_fsub_op.b,%pc,%d1.w*1)
11846 mov.b DST_EX(%a1),%d1
11847 eor.b %d1,%d0
11863 mov.b 3+L_SCR3(%a6),%d1
11864 andi.b &0x30,%d1 # extract rnd mode
11865 cmpi.b %d1,&rm_mode*0x10 # is rnd mode = RM?
11906 mov.b DST_EX(%a1),%d1
11907 eor.b %d1,%d0
11978 clr.w %d1
11979 mov.b STAG(%a6),%d1
11997 fmov.l %fpsr,%d1
11998 or.l %d1,USER_FPSR(%a6) # set N,INEX
12050 fmov.l %fpsr,%d1 # save FPSR
12053 or.l %d1,USER_FPSR(%a6) # save INEX2,N
12058 mov.w FP_SCR0_EX(%a6),%d1 # load sgn,exp
12059 mov.l %d1,%d2 # make a copy
12060 andi.l &0x7fff,%d1 # strip sign
12061 sub.l %d0,%d1 # add scale factor
12063 or.w %d1,%d2 # concat old sign,new exp
12105 fmov.l %fpsr,%d1 # save status
12108 or.l %d1,USER_FPSR(%a6) # save INEX2,N
12111 mov.b FPCR_ENABLE(%a6),%d1
12112 andi.b &0x0b,%d1 # is UNFL or INEX enabled?
12119 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode
12132 mov.w FP_SCR0_EX(%a6),%d1 # load current exponent
12135 mov.l %d1,%d2 # make a copy
12136 andi.l &0x7fff,%d1 # strip sign
12138 sub.l %d0,%d1 # subtract scale factor
12139 addi.l &0x6000,%d1 # add new bias
12140 andi.w &0x7fff,%d1
12141 or.w %d2,%d1 # concat new sign,new exp
12142 mov.w %d1,FP_SCR1_EX(%a6) # insert new exp
12157 fmov.l %fpsr,%d1 # save FPSR
12159 or.l %d1,USER_FPSR(%a6) # save INEX2,N
12164 mov.b FPCR_ENABLE(%a6),%d1
12165 andi.b &0x13,%d1 # is OVFL or INEX enabled?
12174 sne %d1 # set sign param accordingly
12188 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
12189 mov.l %d1,%d2 # make a copy
12190 andi.l &0x7fff,%d1 # strip sign
12192 sub.l %d0,%d1 # add scale factor
12193 subi.l &0x6000,%d1 # subtract bias
12194 andi.w &0x7fff,%d1
12195 or.w %d2,%d1 # concat sign,exp
12196 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
12213 fmov.l %fpsr,%d1 # save status
12216 or.l %d1,USER_FPSR(%a6) # save INEX2,N
12231 cmpi.b %d1,&DENORM # weed out DENORM
12233 cmpi.b %d1,&ZERO # weed out ZERO
12235 cmpi.b %d1,&INF # weed out INF
12237 cmpi.b %d1,&SNAN # weed out SNAN
12269 # fetch_dreg(): fetch register according to index in d1 #
12275 # d1 = index of register to fetch from #
12281 # According to the index value in d1 which can range from zero #
12283 # address register indexes start at 8). D0/D1/A0/A1/A6/A7 are on the #
12288 # this routine leaves d1 intact for subsequent store_dreg calls.
12291 mov.w (tbl_fdreg.b,%pc,%d1.w*2),%d0
12363 # store_dreg_l(): store longword to data register specified by d1 #
12370 # d1 = index of register to fetch from #
12376 # According to the index value in d1, store the longword value #
12377 # in d0 to the corresponding data register. D0/D1 are on the stack #
12384 mov.w (tbl_sdregl.b,%pc,%d1.w*2),%d1
12385 jmp (tbl_sdregl.b,%pc,%d1.w*1)
12424 # store_dreg_w(): store word to data register specified by d1 #
12431 # d1 = index of register to fetch from #
12437 # According to the index value in d1, store the word value #
12438 # in d0 to the corresponding data register. D0/D1 are on the stack #
12445 mov.w (tbl_sdregw.b,%pc,%d1.w*2),%d1
12446 jmp (tbl_sdregw.b,%pc,%d1.w*1)
12485 # store_dreg_b(): store byte to data register specified by d1 #
12492 # d1 = index of register to fetch from #
12498 # According to the index value in d1, store the byte value #
12499 # in d0 to the corresponding data register. D0/D1 are on the stack #
12506 mov.w (tbl_sdregb.b,%pc,%d1.w*2),%d1
12507 jmp (tbl_sdregb.b,%pc,%d1.w*1)
12553 # d1 = index of address register to increment #
12561 # specified by d1. A0/A1/A6/A7 reside on the stack. The rest reside #
12572 mov.w (tbl_iareg.b,%pc,%d1.w*2),%d1
12573 jmp (tbl_iareg.b,%pc,%d1.w*1)
12617 # d1 = index of address register to decrement #
12625 # specified by d1. A0/A1/A6/A7 reside on the stack. The rest reside #
12636 mov.w (tbl_dareg.b,%pc,%d1.w*2),%d1
12637 jmp (tbl_dareg.b,%pc,%d1.w*1)
12927 tst.l %d1 # did dfetch fail?
13043 # 2. Calculate absolute value of exponent in d1 by mul and add.
13052 # (*) d1: accumulator for binary exponent
13065 clr.l %d1 # zero d1 for accumulator
13067 mulu.l &0xa,%d1 # mul partial product by one digit place
13069 add.l %d0,%d1 # d1 = d1 + d0
13074 neg.l %d1 # negate before subtracting
13076 sub.l &16,%d1 # sub to compensate for shift of mant
13078 neg.l %d1 # now negative, make pos and set SE
13082 mov.l %d1,-(%sp) # save exp on stack
13094 # (*) d1: lword counter
13105 mov.l &1,%d1 # word counter, init to 1
13120 mov.l (%a0,%d1.L*4),%d4 # load mantissa lonqword into d4
13130 # then inc d1 (=2) to point to the next long word and reset d3 to 0
13137 addq.l &1,%d1 # inc lw pointer in mantissa
13138 cmp.l %d1,&2 # test for last lw
13182 # (*) d1: zero count
13198 mov.l (%sp),%d1 # load expA for range test
13199 cmp.l %d1,&27 # test is with 27
13203 clr.l %d1 # zero count reg
13207 addq.l &1,%d1 # inc zero count
13211 addq.l &8,%d1 # and inc count by 8
13221 addq.l &1,%d1 # inc digit counter
13224 mov.l %d1,%d0 # copy counter to d2
13225 mov.l (%sp),%d1 # get adjusted exp from memory
13226 sub.l %d0,%d1 # subtract count from exp
13228 neg.l %d1 # now its neg; get abs
13255 clr.l %d1 # clr counter
13260 addq.l &8,%d1 # inc counter by 8
13269 addq.l &1,%d1 # inc digit counter
13272 mov.l %d1,%d0 # copy counter to d0
13273 mov.l (%sp),%d1 # get adjusted exp from memory
13274 sub.l %d0,%d1 # subtract count from exp
13276 neg.l %d1 # take abs of exp and clr SE
13306 # ( ) d1: exponent
13313 # ( ) d1: exponent
13366 mov.l %d1,%d0 # copy exp to d0;use d0
13552 # d1: scratch
13596 mov.l 4(%a0),%d1
13601 roxl.l &1,%d1
13602 tst.l %d1
13613 mov.l %d1,4(%a0)
13808 bfextu USER_FPCR(%a6){&26:&2},%d1 # get initial rmode bits
13809 lsl.w &1,%d1 # put them in bits 2:1
13810 add.w %d5,%d1 # add in LAMBDA
13811 lsl.w &1,%d1 # put them in bits 3:1
13814 addq.l &1,%d1 # if neg, set bit 0
13817 mov.b (%a2,%d1),%d3 # load d3 with new rmode
14018 movm.l &0xc0c0,-(%sp) # save regs used by sintd0 {%d0-%d1/%a0-%a1}
14048 movm.l (%sp)+,&0x303 # restore regs used by sint {%d0-%d1/%a0-%a1}
14174 # d1: x/0
14219 clr.l %d1 # put zero in d1 for addx
14221 addx.l %d1,%d2 # continue inc
14247 # d1: x/scratch (0);shift count for final exponent packing
14304 clr.l %d1 # put zero in d1 for addx
14306 addx.l %d1,%d2 # continue inc
14312 mov.l &12,%d1 # use d1 for shift count
14313 lsr.l %d1,%d0 # shift d0 right by 12
14315 lsr.l %d1,%d0 # shift d0 right by 12
14441 # extracts and shifts. The three msbs from d2 will go into d1. #
14447 # into d2:d3. D1 will contain the bcd digit formed. #
14463 # d1: temp used to form the digit
14489 # A3. Multiply d2:d3 by 8; extract msbs into d1.
14491 bfextu %d2{&0:&3},%d1 # copy 3 msbs of d2 into d1
14497 # A4. Multiply d4:d5 by 2; add carry out to d1.
14502 addx.w %d6,%d1 # add in extend from mul by 2
14504 # A5. Add mul by 8 to mul by 2. D1 contains the digit formed.
14510 addx.w %d6,%d1 # add in extend from add to d1
14520 add.w %d1,%d7 # add in ls digit to d7b
14528 mov.w %d1,%d7 # put new digit in d7b
14653 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
14679 mov.b EXC_OPWORD+0x1(%a6),%d1
14680 andi.b &0x38,%d1 # extract opmode
14681 cmpi.b %d1,&0x18 # postinc?
14683 cmpi.b %d1,&0x20 # predec?
14688 mov.b EXC_OPWORD+0x1(%a6),%d1
14689 andi.w &0x0007,%d1 # fetch An
14691 mov.w (tbl_rest_inc.b,%pc,%d1.w*2),%d1
14692 jmp (tbl_rest_inc.b,%pc,%d1.w*1)