Lines Matching +full:no +full:- +full:pc +full:- +full:write
3 M68000 Hi-Performance Microprocessor Division
5 Production Release P1.00 -- October 10, 1994
17 IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
21 Motorola assumes no responsibility for the maintenance and support of the SOFTWARE.
26 No licenses are granted by implication, estoppel or otherwise under any patents label
98 mov.l %d0,-(%sp)
99 mov.l (_060ISP_TABLE-0x80+_off_chk,%pc),%d0
100 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
106 mov.l %d0,-(%sp)
107 mov.l (_060ISP_TABLE-0x80+_off_divbyzero,%pc),%d0
108 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
114 mov.l %d0,-(%sp)
115 mov.l (_060ISP_TABLE-0x80+_off_trace,%pc),%d0
116 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
122 mov.l %d0,-(%sp)
123 mov.l (_060ISP_TABLE-0x80+_off_access,%pc),%d0
124 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
130 mov.l %d0,-(%sp)
131 mov.l (_060ISP_TABLE-0x80+_off_done,%pc),%d0
132 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
140 mov.l %d0,-(%sp)
141 mov.l (_060ISP_TABLE-0x80+_off_cas,%pc),%d0
142 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
148 mov.l %d0,-(%sp)
149 mov.l (_060ISP_TABLE-0x80+_off_cas2,%pc),%d0
150 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
156 mov.l %d0,-(%sp)
157 mov.l (_060ISP_TABLE-0x80+_off_lock,%pc),%d0
158 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
164 mov.l %d0,-(%sp)
165 mov.l (_060ISP_TABLE-0x80+_off_unlock,%pc),%d0
166 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
174 mov.l %d0,-(%sp)
175 mov.l (_060ISP_TABLE-0x80+_off_imr,%pc),%d0
176 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
182 mov.l %d0,-(%sp)
183 mov.l (_060ISP_TABLE-0x80+_off_dmr,%pc),%d0
184 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
190 mov.l %d0,-(%sp)
191 mov.l (_060ISP_TABLE-0x80+_off_dmw,%pc),%d0
192 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
198 mov.l %d0,-(%sp)
199 mov.l (_060ISP_TABLE-0x80+_off_irw,%pc),%d0
200 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
206 mov.l %d0,-(%sp)
207 mov.l (_060ISP_TABLE-0x80+_off_irl,%pc),%d0
208 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
214 mov.l %d0,-(%sp)
215 mov.l (_060ISP_TABLE-0x80+_off_drb,%pc),%d0
216 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
222 mov.l %d0,-(%sp)
223 mov.l (_060ISP_TABLE-0x80+_off_drw,%pc),%d0
224 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
230 mov.l %d0,-(%sp)
231 mov.l (_060ISP_TABLE-0x80+_off_drl,%pc),%d0
232 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
238 mov.l %d0,-(%sp)
239 mov.l (_060ISP_TABLE-0x80+_off_dwb,%pc),%d0
240 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
246 mov.l %d0,-(%sp)
247 mov.l (_060ISP_TABLE-0x80+_off_dww,%pc),%d0
248 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
254 mov.l %d0,-(%sp)
255 mov.l (_060ISP_TABLE-0x80+_off_dwl,%pc),%d0
256 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
266 set LV, -LOCAL_SIZE # stack offset
269 set EXC_IPC, 0x6 # stack pc
300 set EXC_EXTWPTR, LV+4 # offset of current PC
308 set mda7_flg, 0x08 # -(a7) flag
311 set restore_flg, 0x40 # restore -(an)+ flag
315 set mda7_bit, 0x3 # -(a7) bit
318 set restore_bit, 0x6 # restore -(a7)+ bit
337 # _imem_read_{word,long}() - read instruction word/longword #
338 # _mul64() - emulate 64-bit multiply #
339 # _div64() - emulate 64-bit divide #
340 # _moveperipheral() - emulate "movep" #
341 # _compandset() - emulate misaligned "cas" #
342 # _compandset2() - emulate "cas2" #
343 # _chk2_cmp2() - emulate "cmp2" and "chk2" #
344 # _isp_done() - "callout" for normal final exit #
345 # _real_trace() - "callout" for Trace exception #
346 # _real_chk() - "callout" for Chk exception #
347 # _real_divbyzero() - "callout" for DZ exception #
348 # _real_access() - "callout" for access error exception #
351 # - The system stack contains the Unimp Int Instr stack frame #
355 # - The system stack changed to contain Trace exc stack frame #
357 # - The system stack changed to contain Chk exc stack frame #
359 # - The system stack changed to contain DZ exc stack frame #
361 # - The system stack changed to contain access err exc stk frame #
363 # - Results saved as appropriate #
372 # types of exceptions. "div" can produce a divide-by-zero exception, #
380 # Meanwhile, if any read or write to memory using the #
381 # _mem_{read,write}() "callout"s returns a failing value, then an #
387 # This handler, upon entry, saves almost all user-visible #
399 link.w %a6,&-LOCAL_SIZE # create room for stack frame
401 movm.l &0x3fff,EXC_DREGS(%a6) # store d0-d7/a0-a5
423 # fetch the opword and first extension word pointed to by the stacked pc
485 beq.w uieh_done # no
488 bra.w uieh_a7 # no
500 btst &idbyz_bit,SPCOND_FLG(%a6) # did divide-by-zero occur?
502 bra.w uieh_done # no
505 beq.b uieh_div64_dbyz # no
510 # (iii) (a7)+; divide-by-zero
512 btst &idbyz_bit,SPCOND_FLG(%a6) # did divide-by-zero occur?
514 tst.b EXC_ISR(%a6) # no; is trace enabled?
516 bra.w uieh_a7 # no
542 # the cases of "cas Dc,Du,(a7)+" and "cas Dc,Du,-(a7)" used from supervisor
588 movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
593 mov.l EXC_EXTWPTR(%a6),EXC_IPC(%a6) # new pc on stack frame
608 # ***************** * PC *
610 # * PC * * 0x2 * 0x024 *
613 # ***************** * PC *
614 # ->* Old * *****************
615 # from link -->* A6 * * SR *
617 # /* A7 * * New * <-- for final unlink
624 mov.l EXC_A6(%a6),-0x4(%a6)
637 # ***************** * PC *
639 # * PC * * 0x2 * 0x018 *
642 # ***************** * PC *
654 movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
657 mov.l EXC_IPC(%a6),0x8(%a6) # put "Current PC" on stack
658 mov.l EXC_EXTWPTR(%a6),0x2(%a6) # put "Next PC" on stack
670 # ***************** * PC *
672 # * PC * * 0x2 * 0x014 *
675 # ***************** * PC *
688 movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
691 mov.l EXC_IPC(%a6),0x8(%a6) # put "Current PC" on stack
692 mov.l EXC_EXTWPTR(%a6),0x2(%a6) # put "Next PC" on stack
704 # UIEH FRAME * PC *
709 # * PC * * PC *
725 movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
727 mov.l EXC_IPC(%a6),0xc(%a6) # put "Current PC" on stack
729 mov.l EXC_EXTWPTR(%a6),0x6(%a6) # put "Next PC" on stack
740 # UIEH FRAME * PC *
745 # * PC * * PC *
763 movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
765 mov.l EXC_IPC(%a6),0xc(%a6) # put "Current PC" on stack
767 mov.l EXC_EXTWPTR(%a6),0x6(%a6) # put "Next PC" on stack
780 # * 0x0 * 0x0f4 * * PC *
783 # * PC * *****************
790 movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
793 mov.l EXC_EXTWPTR(%a6),0xa(%a6) # put "Next PC" on stack
802 # this is the exit point if a data read or write fails.
807 mov.l %d0,-0x4(%a6) # save partial fslw
809 lea -64(%a6),%sp
810 movm.l (%sp)+,&0x7fff # restore d0-d7/a0-a6
812 mov.l 0xc(%sp),-(%sp) # move voff,hi(pc)
814 mov.l 0xc(%sp),0x4(%sp) # store sr,lo(pc)
816 mov.l (%sp)+,0x4(%sp) # store voff,hi(pc)
829 movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
832 mov.l 0x8(%sp),(%sp) # store sr,lo(pc)
833 mov.w 0xc(%sp),0x4(%sp) # store hi(pc)
835 mov.l 0x2(%sp),0x8(%sp) # store address (=pc)
845 # if the addressing mode was (an)+ or -(an), the address register must
846 # be restored to its pre-exception value before entering _real_access.
849 bne.b isp_restore_done # no
861 # _imem_read_word() - read instruction word #
862 # _imem_read_long() - read instruction longword #
863 # _dmem_read_long() - read data longword (for memory indirect) #
864 # isp_iacc() - handle instruction access error exception #
865 # isp_dacc() - handle data access error exception #
883 # uses byte-sized operands, only handle word and long operations. #
885 # Dn,An - shouldn't enter here #
886 # (An) - fetch An value from stack #
887 # -(An) - fetch An value from stack; return decr value; #
889 # future access error; if -(a7), set mda7_flg in #
891 # (An)+ - fetch An value from stack; return value; #
895 # (d16,An) - fetch An value from stack; read d16 using #
896 # _imem_read_word(); fetch may fail -> branch to #
898 # (xxx).w,(xxx).l - use _imem_read_{word,long}() to fetch #
900 # #<data> - return address of immediate value; set immed_flg #
902 # (d16,PC) - fetch stacked PC value; read d16 using #
903 # _imem_read_word(); fetch may fail -> branch to #
905 # everything else - read needed displacements as appropriate w/ #
924 mov.w (tbl_ea_mode.b,%pc,%d0.w*2), %d0 # fetch jmp distance
925 jmp (tbl_ea_mode.b,%pc,%d0.w*1) # jmp to correct ea mode
929 short tbl_ea_mode - tbl_ea_mode
930 short tbl_ea_mode - tbl_ea_mode
931 short tbl_ea_mode - tbl_ea_mode
932 short tbl_ea_mode - tbl_ea_mode
933 short tbl_ea_mode - tbl_ea_mode
934 short tbl_ea_mode - tbl_ea_mode
935 short tbl_ea_mode - tbl_ea_mode
936 short tbl_ea_mode - tbl_ea_mode
938 short tbl_ea_mode - tbl_ea_mode
939 short tbl_ea_mode - tbl_ea_mode
940 short tbl_ea_mode - tbl_ea_mode
941 short tbl_ea_mode - tbl_ea_mode
942 short tbl_ea_mode - tbl_ea_mode
943 short tbl_ea_mode - tbl_ea_mode
944 short tbl_ea_mode - tbl_ea_mode
945 short tbl_ea_mode - tbl_ea_mode
947 short addr_ind_a0 - tbl_ea_mode
948 short addr_ind_a1 - tbl_ea_mode
949 short addr_ind_a2 - tbl_ea_mode
950 short addr_ind_a3 - tbl_ea_mode
951 short addr_ind_a4 - tbl_ea_mode
952 short addr_ind_a5 - tbl_ea_mode
953 short addr_ind_a6 - tbl_ea_mode
954 short addr_ind_a7 - tbl_ea_mode
956 short addr_ind_p_a0 - tbl_ea_mode
957 short addr_ind_p_a1 - tbl_ea_mode
958 short addr_ind_p_a2 - tbl_ea_mode
959 short addr_ind_p_a3 - tbl_ea_mode
960 short addr_ind_p_a4 - tbl_ea_mode
961 short addr_ind_p_a5 - tbl_ea_mode
962 short addr_ind_p_a6 - tbl_ea_mode
963 short addr_ind_p_a7 - tbl_ea_mode
965 short addr_ind_m_a0 - tbl_ea_mode
966 short addr_ind_m_a1 - tbl_ea_mode
967 short addr_ind_m_a2 - tbl_ea_mode
968 short addr_ind_m_a3 - tbl_ea_mode
969 short addr_ind_m_a4 - tbl_ea_mode
970 short addr_ind_m_a5 - tbl_ea_mode
971 short addr_ind_m_a6 - tbl_ea_mode
972 short addr_ind_m_a7 - tbl_ea_mode
974 short addr_ind_disp_a0 - tbl_ea_mode
975 short addr_ind_disp_a1 - tbl_ea_mode
976 short addr_ind_disp_a2 - tbl_ea_mode
977 short addr_ind_disp_a3 - tbl_ea_mode
978 short addr_ind_disp_a4 - tbl_ea_mode
979 short addr_ind_disp_a5 - tbl_ea_mode
980 short addr_ind_disp_a6 - tbl_ea_mode
981 short addr_ind_disp_a7 - tbl_ea_mode
983 short _addr_ind_ext - tbl_ea_mode
984 short _addr_ind_ext - tbl_ea_mode
985 short _addr_ind_ext - tbl_ea_mode
986 short _addr_ind_ext - tbl_ea_mode
987 short _addr_ind_ext - tbl_ea_mode
988 short _addr_ind_ext - tbl_ea_mode
989 short _addr_ind_ext - tbl_ea_mode
990 short _addr_ind_ext - tbl_ea_mode
992 short abs_short - tbl_ea_mode
993 short abs_long - tbl_ea_mode
994 short pc_ind - tbl_ea_mode
995 short pc_ind_ext - tbl_ea_mode
996 short immediate - tbl_ea_mode
997 short tbl_ea_mode - tbl_ea_mode
998 short tbl_ea_mode - tbl_ea_mode
999 short tbl_ea_mode - tbl_ea_mode
1040 mov.l %a0,%d0 # copy no. bytes
1051 mov.l %a0,%d0 # copy no. bytes
1062 mov.l %a0,%d0 # copy no. bytes
1073 mov.l %a0,%d0 # copy no. bytes
1084 mov.l %a0,%d0 # copy no. bytes
1095 mov.l %a0,%d0 # copy no. bytes
1106 mov.l %a0,%d0 # copy no. bytes
1119 mov.l %a0,%d0 # copy no. bytes
1126 # Address register indirect w/ predecrement: -(An) #
1314 # Address register indirect w/ index(8-bit displacement): (dn, An, Xn) #
1320 mov.l %d1,-(%sp)
1336 movm.l &0x3c00,-(%sp) # save d2-d5
1344 mov.l %d2,-(%sp) # save old d2
1411 # Program counter indirect w/ displacement: (d16, PC) #
1423 add.l EXC_EXTWPTR(%a6),%a0 # pc + d16
1431 # PC indirect w/ index(8-bit displacement): (d8, PC, An) #
1432 # " " w/ " (base displacement): (bd, PC, An) #
1433 # PC memory indirect postindexed: ([bd, PC], Xn, od) #
1434 # PC memory indirect preindexed: ([bd, PC, Xn], od) #
1452 movm.l &0x3c00,-(%sp) # save d2-d5
1460 mov.l %d2,-(%sp) # create a temp register
1600 movm.l (%sp)+,&0x003c # restore d2-d5
1621 # _dmem_read_byte() - read byte from memory #
1622 # _dmem_write_byte() - write byte to memory #
1623 # isp_dacc() - handle data access error exception #
1637 # either read or write the required bytes from/to memory. Use the #
1638 # _dmem_{read,write}_byte() routines. If one of the memory routines #
1664 # reg2mem: fetch dx, then write it to memory
1683 bsr.l _dmem_write_byte # os : write hi
1693 bsr.l _dmem_write_byte # os : write lo
1703 bsr.l _dmem_write_byte # os : write lo
1713 bsr.l _dmem_write_byte # os : write lo
1727 bsr.l _dmem_write_byte # os : write hi
1736 bsr.l _dmem_write_byte # os : write lo
1831 # if dmem_{read,write}_byte() returns a fail message in d1, the package
1835 # write = true
1883 # If the instruction is chk2 and the Rn value is out-of-bounds, set #
1977 # (1) save 'Z' bit from (Rn - lo)
1978 # (2) save 'Z' and 'N' bits from ((hi - lo) - (Rn - hi))
1983 sub.l %d0, %d2 # (Rn - lo)
1986 sub.l %d0, %d1 # (hi - lo)
1987 cmp.l %d1,%d2 # ((hi - lo) - (Rn - hi))
2040 # 64/32->32r:32q #
2043 # _calc_ea() - calculate effective address #
2044 # isp_iacc() - handle instruction access error exception #
2045 # isp_dacc() - handle data access error exception #
2046 # isp_restore() - restore An on access error w/ -() or ()+ #
2065 # sign info for later. Separate out special cases like divide-by-zero #
2066 # or 32-bit divides if possible. Else, use a special math algorithm #
2134 # - is (dividend == 0) ?
2135 # - is (hi(dividend) == 0 && (divisor <= lo(dividend))) ? (32-bit div)
2138 bne.b dnormaldivide # no, so try it the long way
2156 # - is hi(dividend) >= divisor ? if yes, then overflow
2166 beq.b ddone # divu has no processing!!!
2177 # 0x80000000 is the largest number representable as a 32-bit negative
2179 cmpi.l %d6, &0x80000000 # will (-quot) fit in 32 bits?
2182 neg.l %d6 # make (-quot) 2's comp
2311 mov.l %d6, -(%sp)
2320 sub.l %d3, %d4 # U1U2 - V1q
2330 # add.l %d6, %d4 # (U1U2 - V1q) + U3
2333 bls.b ddadjd1 # is V2q > (U1U2-V1q) + U3 ?
2339 mov.l %d5, -(%sp) # save %d5 (%d6 already saved)
2350 bcc dd2nd # no carry, do next quotient digit
2353 # - according to Knuth, this is done only 2 out of 65536 times for random
2398 # factors for the 32X32->64 multiplication are in %d5 and %d6.
2408 mulu.w %d5, %d6 # %d6 <- lsw*lsw
2409 mulu.w %d3, %d5 # %d5 <- msw-dest*lsw-source
2410 mulu.w %d4, %d2 # %d2 <- msw-source*lsw-dest
2411 mulu.w %d4, %d3 # %d3 <- msw*msw
2464 # (an)+ or -(an) in which case the previous "an" value must be restored.
2478 # _mul64(): routine to emulate mul{u,s}.l <ea>,Dh:Dl 32x32->64 #
2481 # _calc_ea() - calculate effective address #
2482 # isp_iacc() - handle instruction access error exception #
2483 # isp_dacc() - handle data access error exception #
2484 # isp_restore() - restore An on access error w/ -() or ()+ #
2503 # sign info for later. Perform the multiplication using 16x16->32 #
2550 bge.b mul64_chk_md_sgn # no
2557 bge.b mul64_alg # no
2563 # ---------------------------- #
2565 # ---------------------------- #
2566 # ----------------------------- #
2568 # ----------------------------- #
2569 # ----------------------------- #
2571 # ----------------------------- #
2572 # | ----------------------------- #
2573 # --|-- | lo(mplier) * lo(mplicand) | #
2574 # | ----------------------------- #
2576 # -------------------------------------------------------- #
2578 # -------------------------------------------------------- #
2616 beq.b mul64_done # no
2620 # -negate all bits and add 1
2662 # must calculate the <ea> and go fetch the 32-bit operand.
2699 # (an)+ or -(an) in which case the previous "an" value must be restored.
2720 # _real_lock_page() - "callout" to lock op's page from page-outs #
2721 # _cas_terminate2() - access error exit #
2722 # _real_cas2() - "callout" to core cas2 emulation code #
2723 # _real_unlock_page() - "callout" to unlock page #
2746 # using _real_unlock_paged() if the 2nd lock-page fails. #
2751 # Re-perform the comparison so we can determine the condition #
2833 mov.l %d0,-(%sp) # save FSLW
2857 bne.b cas2_finish_w_done # no
2888 bne.b cas2_finish_l_done # no
2957 # d0 = 0 => in range; -1 => out of range #
2974 # Either way, after emulation, the package is re-entered at #
2975 # _isp_cas_finish(). This routine re-compares the operands in order to #
2982 # the emulation sequence should be re-started from the beginning. #
3060 bne.b cas_finish_w_done # no
3081 bne.b cas_finish_l_done # no
3121 mov.l %d0,-(%sp)
3122 bsr.l isp_restore # restore An (if ()+ or -())
3147 lea _CASHI(%pc),%a1 # load end of CAS core code
3148 cmp.l %a1,%a0 # is PC in range?
3149 blt.b cin_no # no
3150 lea _CASLO(%pc),%a1 # load begin of CAS core code
3151 cmp.l %a0,%a1 # is PC in range?
3152 blt.b cin_no # no
3155 mov.l &-0x1,%d0 # out of range; return d0 = -1
3163 # OS if it is too operating system-specific. #
3181 # _isp_cas2_finish() - only exit point for this emulation code; #
3182 # do clean-up; calculate ccodes; store #
3197 # (4) Use "plpaw" instruction to pre-load ATC with effective #
3204 # (6) Use "plpar" instruction to do a re-load of ATC entries for #
3207 # (7) Pre-fetch the core emulation instructions by executing #
3213 # (11)Unequal. No update occurs. But, we do write the DST1 op #
3217 # (13)Write update operand to the DST locations. Use BUSCR to #
3218 # assert LOCKE* for the final write operation. #
3279 # mask interrupts levels 0-6. save old mask value.
3288 # pre-load the operand ATC. no page faults should occur here because
3316 # there are three possible mis-aligned cases for longword cas. they
3317 # are separated because the final write which asserts LOCKE* must
3321 beq.b CAS2L_ENTER # no
3327 # D0 = dst operand 1 <-
3328 # D1 = dst operand 2 <-
3352 cmp.l %d0,%d2 # Dest1 - Compare1
3354 cmp.l %d1,%d3 # Dest2 - Compare2
3356 movs.l %d5,(%a1) # Update2[31:0] -> DEST2
3362 movs.l %d4,(%a0) # Update1[31:0] -> DEST1
3369 movs.l %d0,(%a0) # Dest1[31:0] -> DEST1
3394 # D4 = 'xxxxxx11 -> no reg update; 'xxxxxx00 -> update required #
3417 sf %d4 # indicate no update was done
3443 cmp.l %d0,%d2 # Dest1 - Compare1
3445 cmp.l %d1,%d3 # Dest2 - Compare2
3447 movs.l %d5,(%a1) # Update2[31:0] -> Dest2
3453 movs.w %d4,(%a0)+ # Update1[31:16] -> DEST1
3460 movs.w %d4,(%a0) # Update1[15:0] -> DEST1+0x2
3468 movs.w %d0,(%a0)+ # Dest1[31:16] -> DEST1
3475 movs.w %d0,(%a0) # Dest1[15:0] -> DEST1+0x2
3503 cmp.l %d0,%d2 # Dest1 - Compare1
3505 cmp.l %d1,%d3 # Dest2 - Compare2
3507 movs.l %d5,(%a1) # Update2[31:0] -> DEST2
3513 movs.b %d4,(%a0)+ # Update1[31:24] -> DEST1
3515 movs.w %d4,(%a0)+ # Update1[23:8] -> DEST1+0x1
3522 movs.b %d4,(%a0) # Update1[7:0] -> DEST1+0x3
3537 movs.b %d0,(%a0)+ # Dest1[31:24] -> DEST1
3539 movs.w %d0,(%a0)+ # Dest1[23:8] -> DEST1+0x1
3546 movs.b %d0,(%a0) # Update1[7:0] -> DEST1+0x3
3581 # mask interrupt levels 0-6. save old mask value.
3590 # pre-load the operand ATC. no page faults should occur because
3618 # there are two possible mis-aligned cases for word cas. they
3619 # are separated because the final write which asserts LOCKE* must
3624 bra.b CAS2W_ENTER # no
3627 # D0 = dst operand 1 <-
3628 # D1 = dst operand 2 <-
3652 cmp.w %d0,%d2 # Dest1 - Compare1
3654 cmp.w %d1,%d3 # Dest2 - Compare2
3656 movs.w %d5,(%a1) # Update2[15:0] -> DEST2
3662 movs.w %d4,(%a0) # Update1[15:0] -> DEST1
3669 movs.w %d0,(%a0) # Dest1[15:0] -> DEST1
3694 # D4 = 'xxxxxx11 -> no reg update; 'xxxxxx00 -> update required #
3717 sf %d4 # indicate no update was done
3743 cmp.w %d0,%d2 # Dest1 - Compare1
3745 cmp.w %d1,%d3 # Dest2 - Compare2
3747 movs.w %d5,(%a1) # Update2[15:0] -> DEST2
3753 movs.b %d4,(%a0)+ # Update1[15:8] -> DEST1
3760 movs.b %d4,(%a0) # Update1[7:0] -> DEST1+0x1
3768 movs.b %d0,(%a0)+ # Dest1[15:8] -> DEST1
3775 movs.b %d0,(%a0) # Dest1[7:0] -> DEST1+0x1
3802 # _isp_cas_finish() - only exit point for this emulation code; #
3803 # do clean-up #
3817 # (4) Use "plpaw" instruction to pre-load ATC with effective #
3824 # (6) Pre-fetch the core emulation instructions by executing one #
3830 # (10)Unequal. No update occurs. But, we do write the DST op back #
3834 # (12)Write update operand to the DST location. Use BUSCR to #
3835 # assert LOCKE* for the final write operation. #
3890 # mask interrupt levels 0-6. save old mask value.
3899 # pre-load the operand ATC. no page faults should occur here because
3913 # pre-load the instruction cache for the following algorithm.
3915 bra.b CASW_ENTER # start pre-loading icache
3918 # D0 = dst operand <-
3937 cmp.w %d0,%d4 # Dest - Compare
3944 movs.b %d2,(%a0)+ # Update[15:8] -> DEST
3946 movs.b %d3,(%a0) # Update[7:0] -> DEST+0x1
3961 movs.b %d0,(%a0)+ # Dest[15:8] -> DEST
3968 movs.b %d0,(%a0) # Dest[7:0] -> DEST+0x1
3990 # D1 = 'xxxxxx11 -> no reg update; 'xxxxxx00 -> update required #
4016 sf %d1 # indicate no update was done
4033 # there are two possible mis-aligned cases for longword cas. they
4034 # are separated because the final write which asserts LOCKE* must
4035 # be an aligned write.
4048 # mask interrupts levels 0-6. save old mask value.
4057 # pre-load the operand ATC. no page faults should occur here because
4071 bra.b CASL_ENTER # start pre-loading icache
4074 # D0 = dst operand <-
4093 cmp.l %d0,%d4 # Dest - Compare
4100 movs.w %d2,(%a0)+ # Update[31:16] -> DEST
4102 movs.w %d3,(%a0) # Update[15:0] -> DEST+0x2
4117 movs.w %d0,(%a0)+ # Dest[31:16] -> DEST
4124 movs.w %d0,(%a0) # Dest[15:0] -> DEST+0x2
4146 # D1 = 'xxxxxx11 -> no reg update; 'xxxxxx00 -> update required #
4172 sf %d1 # indicate no update was done
4194 # mask interrupts levels 0-6. save old mask value.
4203 # pre-load the operand ATC. no page faults should occur here because
4217 # pre-load the instruction cache for the following algorithm.
4219 bra.b CASL2_ENTER # start pre-loading icache
4222 # D0 = dst operand <-
4241 cmp.l %d0,%d4 # Dest - Compare
4248 movs.b %d2,(%a0)+ # Update[31:24] -> DEST
4249 movs.w %d3,(%a0)+ # Update[23:8] -> DEST+0x1
4255 movs.b %d5,(%a0) # Update[7:0] -> DEST+0x3
4263 movs.b %d0,(%a0)+ # Dest[31:24] -> DEST
4265 movs.w %d0,(%a0)+ # Dest[23:8] -> DEST+0x1
4272 movs.b %d0,(%a0) # Dest[7:0] -> DEST+0x3