Lines Matching +full:0 +full:x402
18 #define DMA_TIMER_0 (0x00)
19 #define DMA_TIMER_1 (0x40)
20 #define DMA_TIMER_2 (0x80)
21 #define DMA_TIMER_3 (0xc0)
23 #define DTMR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x400)
24 #define DTXMR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x402)
25 #define DTER0 (MCF_IPSBAR + DMA_TIMER_0 + 0x403)
26 #define DTRR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x404)
27 #define DTCR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x408)
28 #define DTCN0 (MCF_IPSBAR + DMA_TIMER_0 + 0x40c)
36 #define DMA_DTMR_ENABLE (1 << 0)
54 * We setup DMA timer 0 in free run mode. This incrementing counter is in init_cf_dt_clocksource()
59 __raw_writeb(0x00, DTXMR0); in init_cf_dt_clocksource()
60 __raw_writeb(0x00, DTER0); in init_cf_dt_clocksource()
61 __raw_writel(0x00000000, DTRR0); in init_cf_dt_clocksource()