Lines Matching +full:0 +full:x392
29 * __asm__ __volatile__("parse_r addr, %0\n\t"
30 * "#invtlb op, 0, %0\n\t"
31 * ".word ((0x6498000) | (addr << 10) | (0 << 5) | op)"
43 _IFC_REG(0) _IFC_REG(1) _IFC_REG(2) _IFC_REG(3)
69 #define REG_ZERO 0x0
70 #define REG_RA 0x1
71 #define REG_TP 0x2
72 #define REG_SP 0x3
73 #define REG_A0 0x4 /* Reused as V0 for return value */
74 #define REG_A1 0x5 /* Reused as V1 for return value */
75 #define REG_A2 0x6
76 #define REG_A3 0x7
77 #define REG_A4 0x8
78 #define REG_A5 0x9
79 #define REG_A6 0xa
80 #define REG_A7 0xb
81 #define REG_T0 0xc
82 #define REG_T1 0xd
83 #define REG_T2 0xe
84 #define REG_T3 0xf
85 #define REG_T4 0x10
86 #define REG_T5 0x11
87 #define REG_T6 0x12
88 #define REG_T7 0x13
89 #define REG_T8 0x14
90 #define REG_U0 0x15 /* Kernel uses it as percpu base */
91 #define REG_FP 0x16
92 #define REG_S0 0x17
93 #define REG_S1 0x18
94 #define REG_S2 0x19
95 #define REG_S3 0x1a
96 #define REG_S4 0x1b
97 #define REG_S5 0x1c
98 #define REG_S6 0x1d
99 #define REG_S7 0x1e
100 #define REG_S8 0x1f
105 #define LOONGARCH_CPUCFG0 0x0
106 #define CPUCFG0_PRID GENMASK(31, 0)
108 #define LOONGARCH_CPUCFG1 0x1
109 #define CPUCFG1_ISGR32 BIT(0)
123 #define LOONGARCH_CPUCFG2 0x2
124 #define CPUCFG2_FP BIT(0)
142 #define LOONGARCH_CPUCFG3 0x3
143 #define CPUCFG3_CCDMA BIT(0)
156 #define LOONGARCH_CPUCFG4 0x4
157 #define CPUCFG4_CCFREQ GENMASK(31, 0)
159 #define LOONGARCH_CPUCFG5 0x5
160 #define CPUCFG5_CCMUL GENMASK(15, 0)
163 #define LOONGARCH_CPUCFG6 0x6
164 #define CPUCFG6_PMP BIT(0)
170 #define LOONGARCH_CPUCFG16 0x10
171 #define CPUCFG16_L1_IUPRE BIT(0)
189 #define LOONGARCH_CPUCFG17 0x11
190 #define LOONGARCH_CPUCFG18 0x12
191 #define LOONGARCH_CPUCFG19 0x13
192 #define LOONGARCH_CPUCFG20 0x14
193 #define CPUCFG_CACHE_WAYS_M GENMASK(15, 0)
196 #define CPUCFG_CACHE_WAYS 0
200 #define LOONGARCH_CPUCFG48 0x30
201 #define CPUCFG48_MCSR_LCK BIT(0)
265 #define LOONGARCH_CSR_CRMD 0x0 /* Current mode info */
267 #define CSR_CRMD_WE (_ULCAST_(0x1) << CSR_CRMD_WE_SHIFT)
270 #define CSR_CRMD_DACM (_ULCAST_(0x3) << CSR_CRMD_DACM_SHIFT)
273 #define CSR_CRMD_DACF (_ULCAST_(0x3) << CSR_CRMD_DACF_SHIFT)
275 #define CSR_CRMD_PG (_ULCAST_(0x1) << CSR_CRMD_PG_SHIFT)
277 #define CSR_CRMD_DA (_ULCAST_(0x1) << CSR_CRMD_DA_SHIFT)
279 #define CSR_CRMD_IE (_ULCAST_(0x1) << CSR_CRMD_IE_SHIFT)
280 #define CSR_CRMD_PLV_SHIFT 0
282 #define CSR_CRMD_PLV (_ULCAST_(0x3) << CSR_CRMD_PLV_SHIFT)
284 #define PLV_KERN 0
286 #define PLV_MASK 0x3
288 #define LOONGARCH_CSR_PRMD 0x1 /* Prev-exception mode info */
290 #define CSR_PRMD_PWE (_ULCAST_(0x1) << CSR_PRMD_PWE_SHIFT)
292 #define CSR_PRMD_PIE (_ULCAST_(0x1) << CSR_PRMD_PIE_SHIFT)
293 #define CSR_PRMD_PPLV_SHIFT 0
295 #define CSR_PRMD_PPLV (_ULCAST_(0x3) << CSR_PRMD_PPLV_SHIFT)
297 #define LOONGARCH_CSR_EUEN 0x2 /* Extended unit enable */
299 #define CSR_EUEN_LBTEN (_ULCAST_(0x1) << CSR_EUEN_LBTEN_SHIFT)
301 #define CSR_EUEN_LASXEN (_ULCAST_(0x1) << CSR_EUEN_LASXEN_SHIFT)
303 #define CSR_EUEN_LSXEN (_ULCAST_(0x1) << CSR_EUEN_LSXEN_SHIFT)
304 #define CSR_EUEN_FPEN_SHIFT 0
305 #define CSR_EUEN_FPEN (_ULCAST_(0x1) << CSR_EUEN_FPEN_SHIFT)
307 #define LOONGARCH_CSR_MISC 0x3 /* Misc config */
309 #define LOONGARCH_CSR_ECFG 0x4 /* Exception config */
312 #define CSR_ECFG_VS (_ULCAST_(0x7) << CSR_ECFG_VS_SHIFT)
313 #define CSR_ECFG_IM_SHIFT 0
315 #define CSR_ECFG_IM (_ULCAST_(0x1fff) << CSR_ECFG_IM_SHIFT)
317 #define LOONGARCH_CSR_ESTAT 0x5 /* Exception status */
320 #define CSR_ESTAT_ESUBCODE (_ULCAST_(0x1ff) << CSR_ESTAT_ESUBCODE_SHIFT)
323 #define CSR_ESTAT_EXC (_ULCAST_(0x3f) << CSR_ESTAT_EXC_SHIFT)
324 #define CSR_ESTAT_IS_SHIFT 0
326 #define CSR_ESTAT_IS (_ULCAST_(0x7fff) << CSR_ESTAT_IS_SHIFT)
328 #define LOONGARCH_CSR_ERA 0x6 /* ERA */
330 #define LOONGARCH_CSR_BADV 0x7 /* Bad virtual address */
332 #define LOONGARCH_CSR_BADI 0x8 /* Bad instruction */
334 #define LOONGARCH_CSR_EENTRY 0xc /* Exception entry */
337 #define LOONGARCH_CSR_TLBIDX 0x10 /* TLB Index, EHINV, PageSize, NP */
342 #define CSR_TLBIDX_PS (_ULCAST_(0x3f) << CSR_TLBIDX_PS_SHIFT)
343 #define CSR_TLBIDX_IDX_SHIFT 0
345 #define CSR_TLBIDX_IDX (_ULCAST_(0xfff) << CSR_TLBIDX_IDX_SHIFT)
346 #define CSR_TLBIDX_SIZEM 0x3f000000
348 #define CSR_TLBIDX_IDXM 0xfff
351 #define LOONGARCH_CSR_TLBEHI 0x11 /* TLB EntryHi */
353 #define LOONGARCH_CSR_TLBELO0 0x12 /* TLB EntryLo0 */
355 #define CSR_TLBLO0_RPLV (_ULCAST_(0x1) << CSR_TLBLO0_RPLV_SHIFT)
357 #define CSR_TLBLO0_NX (_ULCAST_(0x1) << CSR_TLBLO0_NX_SHIFT)
359 #define CSR_TLBLO0_NR (_ULCAST_(0x1) << CSR_TLBLO0_NR_SHIFT)
362 #define CSR_TLBLO0_PFN (_ULCAST_(0xfffffffff) << CSR_TLBLO0_PFN_SHIFT)
364 #define CSR_TLBLO0_GLOBAL (_ULCAST_(0x1) << CSR_TLBLO0_GLOBAL_SHIFT)
367 #define CSR_TLBLO0_CCA (_ULCAST_(0x3) << CSR_TLBLO0_CCA_SHIFT)
370 #define CSR_TLBLO0_PLV (_ULCAST_(0x3) << CSR_TLBLO0_PLV_SHIFT)
372 #define CSR_TLBLO0_WE (_ULCAST_(0x1) << CSR_TLBLO0_WE_SHIFT)
373 #define CSR_TLBLO0_V_SHIFT 0
374 #define CSR_TLBLO0_V (_ULCAST_(0x1) << CSR_TLBLO0_V_SHIFT)
376 #define LOONGARCH_CSR_TLBELO1 0x13 /* TLB EntryLo1 */
378 #define CSR_TLBLO1_RPLV (_ULCAST_(0x1) << CSR_TLBLO1_RPLV_SHIFT)
380 #define CSR_TLBLO1_NX (_ULCAST_(0x1) << CSR_TLBLO1_NX_SHIFT)
382 #define CSR_TLBLO1_NR (_ULCAST_(0x1) << CSR_TLBLO1_NR_SHIFT)
385 #define CSR_TLBLO1_PFN (_ULCAST_(0xfffffffff) << CSR_TLBLO1_PFN_SHIFT)
387 #define CSR_TLBLO1_GLOBAL (_ULCAST_(0x1) << CSR_TLBLO1_GLOBAL_SHIFT)
390 #define CSR_TLBLO1_CCA (_ULCAST_(0x3) << CSR_TLBLO1_CCA_SHIFT)
393 #define CSR_TLBLO1_PLV (_ULCAST_(0x3) << CSR_TLBLO1_PLV_SHIFT)
395 #define CSR_TLBLO1_WE (_ULCAST_(0x1) << CSR_TLBLO1_WE_SHIFT)
396 #define CSR_TLBLO1_V_SHIFT 0
397 #define CSR_TLBLO1_V (_ULCAST_(0x1) << CSR_TLBLO1_V_SHIFT)
399 #define LOONGARCH_CSR_GTLBC 0x15 /* Guest TLB control */
402 #define CSR_GTLBC_RID (_ULCAST_(0xff) << CSR_GTLBC_RID_SHIFT)
404 #define CSR_GTLBC_TOTI (_ULCAST_(0x1) << CSR_GTLBC_TOTI_SHIFT)
406 #define CSR_GTLBC_USERID (_ULCAST_(0x1) << CSR_GTLBC_USERID_SHIFT)
407 #define CSR_GTLBC_GMTLBSZ_SHIFT 0
409 #define CSR_GTLBC_GMTLBSZ (_ULCAST_(0x3f) << CSR_GTLBC_GMTLBSZ_SHIFT)
411 #define LOONGARCH_CSR_TRGP 0x16 /* TLBR read guest info */
414 #define CSR_TRGP_RID (_ULCAST_(0xff) << CSR_TRGP_RID_SHIFT)
415 #define CSR_TRGP_GTLB_SHIFT 0
418 #define LOONGARCH_CSR_ASID 0x18 /* ASID */
421 #define CSR_ASID_BIT (_ULCAST_(0xff) << CSR_ASID_BIT_SHIFT)
422 #define CSR_ASID_ASID_SHIFT 0
424 #define CSR_ASID_ASID (_ULCAST_(0x3ff) << CSR_ASID_ASID_SHIFT)
426 #define LOONGARCH_CSR_PGDL 0x19 /* Page table base address when VA[47] = 0 */
428 #define LOONGARCH_CSR_PGDH 0x1a /* Page table base address when VA[47] = 1 */
430 #define LOONGARCH_CSR_PGD 0x1b /* Page table base */
432 #define LOONGARCH_CSR_PWCTL0 0x1c /* PWCtl0 */
435 #define CSR_PWCTL0_PTEW (_ULCAST_(0x3) << CSR_PWCTL0_PTEW_SHIFT)
438 #define CSR_PWCTL0_DIR1WIDTH (_ULCAST_(0x1f) << CSR_PWCTL0_DIR1WIDTH_SHIFT)
441 #define CSR_PWCTL0_DIR1BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR1BASE_SHIFT)
444 #define CSR_PWCTL0_DIR0WIDTH (_ULCAST_(0x1f) << CSR_PWCTL0_DIR0WIDTH_SHIFT)
447 #define CSR_PWCTL0_DIR0BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR0BASE_SHIFT)
450 #define CSR_PWCTL0_PTWIDTH (_ULCAST_(0x1f) << CSR_PWCTL0_PTWIDTH_SHIFT)
451 #define CSR_PWCTL0_PTBASE_SHIFT 0
453 #define CSR_PWCTL0_PTBASE (_ULCAST_(0x1f) << CSR_PWCTL0_PTBASE_SHIFT)
455 #define LOONGARCH_CSR_PWCTL1 0x1d /* PWCtl1 */
458 #define CSR_PWCTL1_DIR3WIDTH (_ULCAST_(0x1f) << CSR_PWCTL1_DIR3WIDTH_SHIFT)
461 #define CSR_PWCTL1_DIR3BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR3BASE_SHIFT)
464 #define CSR_PWCTL1_DIR2WIDTH (_ULCAST_(0x1f) << CSR_PWCTL1_DIR2WIDTH_SHIFT)
465 #define CSR_PWCTL1_DIR2BASE_SHIFT 0
467 #define CSR_PWCTL1_DIR2BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR2BASE_SHIFT)
469 #define LOONGARCH_CSR_STLBPGSIZE 0x1e
471 #define CSR_STLBPGSIZE_PS (_ULCAST_(0x3f))
473 #define LOONGARCH_CSR_RVACFG 0x1f
475 #define CSR_RVACFG_RDVA (_ULCAST_(0xf))
478 #define LOONGARCH_CSR_CPUID 0x20 /* CPU core id */
480 #define CSR_CPUID_COREID _ULCAST_(0x1ff)
482 #define LOONGARCH_CSR_PRCFG1 0x21 /* Config1 */
488 #define CSR_CONF1_TMRBITS (_ULCAST_(0xff) << CSR_CONF1_TMRBITS_SHIFT)
490 #define CSR_CONF1_KSNUM _ULCAST_(0xf)
492 #define LOONGARCH_CSR_PRCFG2 0x22 /* Config2 */
493 #define CSR_CONF2_PGMASK_SUPP 0x3ffff000
495 #define LOONGARCH_CSR_PRCFG3 0x23 /* Config3 */
498 #define CSR_CONF3_STLBIDX (_ULCAST_(0x3f) << CSR_CONF3_STLBIDX_SHIFT)
501 #define CSR_CONF3_STLBWAYS (_ULCAST_(0xff) << CSR_CONF3_STLBWAYS_SHIFT)
504 #define CSR_CONF3_MTLBSIZE (_ULCAST_(0xff) << CSR_CONF3_MTLBSIZE_SHIFT)
505 #define CSR_CONF3_TLBTYPE_SHIFT 0
507 #define CSR_CONF3_TLBTYPE (_ULCAST_(0xf) << CSR_CONF3_TLBTYPE_SHIFT)
510 #define LOONGARCH_CSR_KS0 0x30
511 #define LOONGARCH_CSR_KS1 0x31
512 #define LOONGARCH_CSR_KS2 0x32
513 #define LOONGARCH_CSR_KS3 0x33
514 #define LOONGARCH_CSR_KS4 0x34
515 #define LOONGARCH_CSR_KS5 0x35
516 #define LOONGARCH_CSR_KS6 0x36
517 #define LOONGARCH_CSR_KS7 0x37
518 #define LOONGARCH_CSR_KS8 0x38
524 #define EXC_KSAVE_MASK (1 << 0 | 1 << 1 | 1 << 2)
536 #define LOONGARCH_CSR_TMID 0x40 /* Timer ID */
538 #define LOONGARCH_CSR_TCFG 0x41 /* Timer config */
541 #define CSR_TCFG_VAL (_ULCAST_(0x3fffffffffff) << CSR_TCFG_VAL_SHIFT)
543 #define CSR_TCFG_PERIOD (_ULCAST_(0x1) << CSR_TCFG_PERIOD_SHIFT)
544 #define CSR_TCFG_EN (_ULCAST_(0x1))
546 #define LOONGARCH_CSR_TVAL 0x42 /* Timer value */
548 #define LOONGARCH_CSR_CNTC 0x43 /* Timer offset */
550 #define LOONGARCH_CSR_TINTCLR 0x44 /* Timer interrupt clear */
551 #define CSR_TINTCLR_TI_SHIFT 0
555 #define LOONGARCH_CSR_GSTAT 0x50 /* Guest status */
558 #define CSR_GSTAT_GID (_ULCAST_(0xff) << CSR_GSTAT_GID_SHIFT)
561 #define CSR_GSTAT_GIDBIT (_ULCAST_(0x3f) << CSR_GSTAT_GIDBIT_SHIFT)
563 #define CSR_GSTAT_PVM (_ULCAST_(0x1) << CSR_GSTAT_PVM_SHIFT)
564 #define CSR_GSTAT_VM_SHIFT 0
565 #define CSR_GSTAT_VM (_ULCAST_(0x1) << CSR_GSTAT_VM_SHIFT)
567 #define LOONGARCH_CSR_GCFG 0x51 /* Guest config */
570 #define CSR_GCFG_GPERF (_ULCAST_(0x7) << CSR_GCFG_GPERF_SHIFT)
573 #define CSR_GCFG_GCI (_ULCAST_(0x3) << CSR_GCFG_GCI_SHIFT)
574 #define CSR_GCFG_GCI_ALL (_ULCAST_(0x0) << CSR_GCFG_GCI_SHIFT)
575 #define CSR_GCFG_GCI_HIT (_ULCAST_(0x1) << CSR_GCFG_GCI_SHIFT)
576 #define CSR_GCFG_GCI_SECURE (_ULCAST_(0x2) << CSR_GCFG_GCI_SHIFT)
578 #define CSR_GCFG_GCIP (_ULCAST_(0xf) << CSR_GCFG_GCIP_SHIFT)
579 #define CSR_GCFG_GCIP_ALL (_ULCAST_(0x1) << CSR_GCFG_GCIP_SHIFT)
580 #define CSR_GCFG_GCIP_HIT (_ULCAST_(0x1) << (CSR_GCFG_GCIP_SHIFT + 1))
581 #define CSR_GCFG_GCIP_SECURE (_ULCAST_(0x1) << (CSR_GCFG_GCIP_SHIFT + 2))
583 #define CSR_GCFG_TORU (_ULCAST_(0x1) << CSR_GCFG_TORU_SHIFT)
585 #define CSR_GCFG_TORUP (_ULCAST_(0x1) << CSR_GCFG_TORUP_SHIFT)
587 #define CSR_GCFG_TOP (_ULCAST_(0x1) << CSR_GCFG_TOP_SHIFT)
589 #define CSR_GCFG_TOPP (_ULCAST_(0x1) << CSR_GCFG_TOPP_SHIFT)
591 #define CSR_GCFG_TOE (_ULCAST_(0x1) << CSR_GCFG_TOE_SHIFT)
593 #define CSR_GCFG_TOEP (_ULCAST_(0x1) << CSR_GCFG_TOEP_SHIFT)
595 #define CSR_GCFG_TIT (_ULCAST_(0x1) << CSR_GCFG_TIT_SHIFT)
597 #define CSR_GCFG_TITP (_ULCAST_(0x1) << CSR_GCFG_TITP_SHIFT)
599 #define CSR_GCFG_SIT (_ULCAST_(0x1) << CSR_GCFG_SIT_SHIFT)
601 #define CSR_GCFG_SITP (_ULCAST_(0x1) << CSR_GCFG_SITP_SHIFT)
604 #define CSR_GCFG_MATC_MASK (_ULCAST_(0x3) << CSR_GCFG_MATC_SHITF)
605 #define CSR_GCFG_MATC_GUEST (_ULCAST_(0x0) << CSR_GCFG_MATC_SHITF)
606 #define CSR_GCFG_MATC_ROOT (_ULCAST_(0x1) << CSR_GCFG_MATC_SHITF)
607 #define CSR_GCFG_MATC_NEST (_ULCAST_(0x2) << CSR_GCFG_MATC_SHITF)
609 #define LOONGARCH_CSR_GINTC 0x52 /* Guest interrupt control */
612 #define CSR_GINTC_HC (_ULCAST_(0xff) << CSR_GINTC_HC_SHIFT)
615 #define CSR_GINTC_PIP (_ULCAST_(0xff) << CSR_GINTC_PIP_SHIFT)
616 #define CSR_GINTC_VIP_SHIFT 0
618 #define CSR_GINTC_VIP (_ULCAST_(0xff))
620 #define LOONGARCH_CSR_GCNTC 0x53 /* Guest timer offset */
623 #define LOONGARCH_CSR_LLBCTL 0x60 /* LLBit control */
624 #define CSR_LLBCTL_ROLLB_SHIFT 0
632 #define LOONGARCH_CSR_IMPCTL1 0x80 /* Loongson config1 */
635 #define CSR_MISPEC (_ULCAST_(0xff) << CSR_MISPEC_SHIFT)
671 #define CSR_DATAPRE_SHIFT 0
674 #define LOONGARCH_CSR_IMPCTL2 0x81 /* Loongson config2 */
675 #define CSR_FLUSH_MTLB_SHIFT 0
686 #define LOONGARCH_CSR_GNMI 0x82
689 #define LOONGARCH_CSR_TLBRENTRY 0x88 /* TLB refill exception entry */
690 #define LOONGARCH_CSR_TLBRBADV 0x89 /* TLB refill badvaddr */
691 #define LOONGARCH_CSR_TLBRERA 0x8a /* TLB refill ERA */
692 #define LOONGARCH_CSR_TLBRSAVE 0x8b /* KSave for TLB refill exception */
693 #define LOONGARCH_CSR_TLBRELO0 0x8c /* TLB refill entrylo0 */
694 #define LOONGARCH_CSR_TLBRELO1 0x8d /* TLB refill entrylo1 */
695 #define LOONGARCH_CSR_TLBREHI 0x8e /* TLB refill entryhi */
696 #define CSR_TLBREHI_PS_SHIFT 0
697 #define CSR_TLBREHI_PS (_ULCAST_(0x3f) << CSR_TLBREHI_PS_SHIFT)
698 #define LOONGARCH_CSR_TLBRPRMD 0x8f /* TLB refill mode info */
701 #define LOONGARCH_CSR_MERRCTL 0x90 /* MERRCTL */
702 #define LOONGARCH_CSR_MERRINFO1 0x91 /* MError info1 */
703 #define LOONGARCH_CSR_MERRINFO2 0x92 /* MError info2 */
704 #define LOONGARCH_CSR_MERRENTRY 0x93 /* MError exception entry */
705 #define LOONGARCH_CSR_MERRERA 0x94 /* MError exception ERA */
706 #define LOONGARCH_CSR_MERRSAVE 0x95 /* KSave for machine error exception */
708 #define LOONGARCH_CSR_CTAG 0x98 /* TagLo + TagHi */
710 #define LOONGARCH_CSR_PRID 0xc0
712 /* Shadow MCSR : 0xc0 ~ 0xff */
713 #define LOONGARCH_CSR_MCSR0 0xc0 /* CPUCFG0 and CPUCFG1 */
715 #define MCSR0_INT_IMPL 0
730 #define MCSR0_VABIT (_ULCAST_(0xff) << MCSR0_VABIT_SHIFT)
731 #define VABIT_DEFAULT 0x2f
734 #define MCSR0_PABIT (_ULCAST_(0xff) << MCSR0_PABIT_SHIFT)
735 #define PABIT_DEFAULT 0x2f
745 #define GR32_DEFAULT 0
747 #define MCSR0_PRID 0x14C010
749 #define LOONGARCH_CSR_MCSR1 0xc1 /* CPUCFG2 and CPUCFG3 */
806 #define MCSR1_FP_SHIFT 0
809 #define LOONGARCH_CSR_MCSR2 0xc2 /* CPUCFG4 and CPUCFG5 */
812 #define MCSR2_CCDIV (_ULCAST_(0xffff) << MCSR2_CCDIV_SHIFT)
815 #define MCSR2_CCMUL (_ULCAST_(0xffff) << MCSR2_CCMUL_SHIFT)
817 #define MCSR2_CCFREQ (_ULCAST_(0xffffffff))
818 #define CCFREQ_DEFAULT 0x5f5e100 /* 100MHz */
820 #define LOONGARCH_CSR_MCSR3 0xc3 /* CPUCFG6 */
825 #define MCSR3_PMBITS (_ULCAST_(0x3f) << MCSR3_PMBITS_SHIFT)
826 #define PMBITS_DEFAULT 0x40
829 #define MCSR3_PMNUM (_ULCAST_(0xf) << MCSR3_PMNUM_SHIFT)
832 #define MCSR3_PAMVER (_ULCAST_(0x7) << MCSR3_PAMVER_SHIFT)
833 #define MCSR3_PMP_SHIFT 0
836 #define LOONGARCH_CSR_MCSR8 0xc8 /* CPUCFG16 and CPUCFG17 */
839 #define MCSR8_L1I_SIZE (_ULCAST_(0x7f) << MCSR8_L1I_SIZE_SHIFT)
842 #define MCSR8_L1I_IDX (_ULCAST_(0xff) << MCSR8_L1I_IDX_SHIFT)
845 #define MCSR8_L1I_WAY (_ULCAST_(0xffff) << MCSR8_L1I_WAY_SHIFT)
878 #define MCSR8_L1IUPRE_SHIFT 0
881 #define LOONGARCH_CSR_MCSR9 0xc9 /* CPUCFG18 and CPUCFG19 */
884 #define MCSR9_L2U_SIZE (_ULCAST_(0x7f) << MCSR9_L2U_SIZE_SHIFT)
887 #define MCSR9_L2U_IDX (_ULCAST_(0xff) << MCSR9_IDX_LOG_SHIFT)
890 #define MCSR9_L2U_WAY (_ULCAST_(0xffff) << MCSR9_L2U_WAY_SHIFT)
893 #define MCSR9_L1D_SIZE (_ULCAST_(0x7f) << MCSR9_L1D_SIZE_SHIFT)
896 #define MCSR9_L1D_IDX (_ULCAST_(0xff) << MCSR9_L1D_IDX_SHIFT)
897 #define MCSR9_L1D_WAY_SHIFT 0
899 #define MCSR9_L1D_WAY (_ULCAST_(0xffff) << MCSR9_L1D_WAY_SHIFT)
901 #define LOONGARCH_CSR_MCSR10 0xca /* CPUCFG20 */
904 #define MCSR10_L3U_SIZE (_ULCAST_(0x7f) << MCSR10_L3U_SIZE_SHIFT)
907 #define MCSR10_L3U_IDX (_ULCAST_(0xff) << MCSR10_L3U_IDX_SHIFT)
908 #define MCSR10_L3U_WAY_SHIFT 0
910 #define MCSR10_L3U_WAY (_ULCAST_(0xffff) << MCSR10_L3U_WAY_SHIFT)
912 #define LOONGARCH_CSR_MCSR24 0xf0 /* cpucfg48 */
919 #define MCSR24_MCSRLOCK_SHIFT 0
923 #define LOONGARCH_CSR_UCAWIN 0x100
924 #define LOONGARCH_CSR_UCAWIN0_LO 0x102
925 #define LOONGARCH_CSR_UCAWIN0_HI 0x103
926 #define LOONGARCH_CSR_UCAWIN1_LO 0x104
927 #define LOONGARCH_CSR_UCAWIN1_HI 0x105
928 #define LOONGARCH_CSR_UCAWIN2_LO 0x106
929 #define LOONGARCH_CSR_UCAWIN2_HI 0x107
930 #define LOONGARCH_CSR_UCAWIN3_LO 0x108
931 #define LOONGARCH_CSR_UCAWIN3_HI 0x109
934 #define LOONGARCH_CSR_DMWIN0 0x180 /* 64 direct map win0: MEM & IF */
935 #define LOONGARCH_CSR_DMWIN1 0x181 /* 64 direct map win1: MEM & IF */
936 #define LOONGARCH_CSR_DMWIN2 0x182 /* 64 direct map win2: MEM */
937 #define LOONGARCH_CSR_DMWIN3 0x183 /* 64 direct map win3: MEM */
939 /* Direct Map window 0/1 */
940 #define CSR_DMW0_PLV0 _CONST64_(1 << 0)
941 #define CSR_DMW0_VSEG _CONST64_(0x8000)
945 #define CSR_DMW1_PLV0 _CONST64_(1 << 0)
947 #define CSR_DMW1_VSEG _CONST64_(0x9000)
952 #define LOONGARCH_CSR_PERFCTRL0 0x200 /* 32 perf event 0 config */
953 #define LOONGARCH_CSR_PERFCNTR0 0x201 /* 64 perf event 0 count value */
954 #define LOONGARCH_CSR_PERFCTRL1 0x202 /* 32 perf event 1 config */
955 #define LOONGARCH_CSR_PERFCNTR1 0x203 /* 64 perf event 1 count value */
956 #define LOONGARCH_CSR_PERFCTRL2 0x204 /* 32 perf event 2 config */
957 #define LOONGARCH_CSR_PERFCNTR2 0x205 /* 64 perf event 2 count value */
958 #define LOONGARCH_CSR_PERFCTRL3 0x206 /* 32 perf event 3 config */
959 #define LOONGARCH_CSR_PERFCNTR3 0x207 /* 64 perf event 3 count value */
965 #define CSR_PERFCTRL_EVENT 0x3ff
968 #define LOONGARCH_CSR_MWPC 0x300 /* data breakpoint config */
969 #define LOONGARCH_CSR_MWPS 0x301 /* data breakpoint status */
971 #define LOONGARCH_CSR_DB0ADDR 0x310 /* data breakpoint 0 address */
972 #define LOONGARCH_CSR_DB0MASK 0x311 /* data breakpoint 0 mask */
973 #define LOONGARCH_CSR_DB0CTL 0x312 /* data breakpoint 0 control */
974 #define LOONGARCH_CSR_DB0ASID 0x313 /* data breakpoint 0 asid */
976 #define LOONGARCH_CSR_DB1ADDR 0x318 /* data breakpoint 1 address */
977 #define LOONGARCH_CSR_DB1MASK 0x319 /* data breakpoint 1 mask */
978 #define LOONGARCH_CSR_DB1CTL 0x31a /* data breakpoint 1 control */
979 #define LOONGARCH_CSR_DB1ASID 0x31b /* data breakpoint 1 asid */
981 #define LOONGARCH_CSR_DB2ADDR 0x320 /* data breakpoint 2 address */
982 #define LOONGARCH_CSR_DB2MASK 0x321 /* data breakpoint 2 mask */
983 #define LOONGARCH_CSR_DB2CTL 0x322 /* data breakpoint 2 control */
984 #define LOONGARCH_CSR_DB2ASID 0x323 /* data breakpoint 2 asid */
986 #define LOONGARCH_CSR_DB3ADDR 0x328 /* data breakpoint 3 address */
987 #define LOONGARCH_CSR_DB3MASK 0x329 /* data breakpoint 3 mask */
988 #define LOONGARCH_CSR_DB3CTL 0x32a /* data breakpoint 3 control */
989 #define LOONGARCH_CSR_DB3ASID 0x32b /* data breakpoint 3 asid */
991 #define LOONGARCH_CSR_DB4ADDR 0x330 /* data breakpoint 4 address */
992 #define LOONGARCH_CSR_DB4MASK 0x331 /* data breakpoint 4 maks */
993 #define LOONGARCH_CSR_DB4CTL 0x332 /* data breakpoint 4 control */
994 #define LOONGARCH_CSR_DB4ASID 0x333 /* data breakpoint 4 asid */
996 #define LOONGARCH_CSR_DB5ADDR 0x338 /* data breakpoint 5 address */
997 #define LOONGARCH_CSR_DB5MASK 0x339 /* data breakpoint 5 mask */
998 #define LOONGARCH_CSR_DB5CTL 0x33a /* data breakpoint 5 control */
999 #define LOONGARCH_CSR_DB5ASID 0x33b /* data breakpoint 5 asid */
1001 #define LOONGARCH_CSR_DB6ADDR 0x340 /* data breakpoint 6 address */
1002 #define LOONGARCH_CSR_DB6MASK 0x341 /* data breakpoint 6 mask */
1003 #define LOONGARCH_CSR_DB6CTL 0x342 /* data breakpoint 6 control */
1004 #define LOONGARCH_CSR_DB6ASID 0x343 /* data breakpoint 6 asid */
1006 #define LOONGARCH_CSR_DB7ADDR 0x348 /* data breakpoint 7 address */
1007 #define LOONGARCH_CSR_DB7MASK 0x349 /* data breakpoint 7 mask */
1008 #define LOONGARCH_CSR_DB7CTL 0x34a /* data breakpoint 7 control */
1009 #define LOONGARCH_CSR_DB7ASID 0x34b /* data breakpoint 7 asid */
1011 #define LOONGARCH_CSR_FWPC 0x380 /* instruction breakpoint config */
1012 #define LOONGARCH_CSR_FWPS 0x381 /* instruction breakpoint status */
1014 #define LOONGARCH_CSR_IB0ADDR 0x390 /* inst breakpoint 0 address */
1015 #define LOONGARCH_CSR_IB0MASK 0x391 /* inst breakpoint 0 mask */
1016 #define LOONGARCH_CSR_IB0CTL 0x392 /* inst breakpoint 0 control */
1017 #define LOONGARCH_CSR_IB0ASID 0x393 /* inst breakpoint 0 asid */
1019 #define LOONGARCH_CSR_IB1ADDR 0x398 /* inst breakpoint 1 address */
1020 #define LOONGARCH_CSR_IB1MASK 0x399 /* inst breakpoint 1 mask */
1021 #define LOONGARCH_CSR_IB1CTL 0x39a /* inst breakpoint 1 control */
1022 #define LOONGARCH_CSR_IB1ASID 0x39b /* inst breakpoint 1 asid */
1024 #define LOONGARCH_CSR_IB2ADDR 0x3a0 /* inst breakpoint 2 address */
1025 #define LOONGARCH_CSR_IB2MASK 0x3a1 /* inst breakpoint 2 mask */
1026 #define LOONGARCH_CSR_IB2CTL 0x3a2 /* inst breakpoint 2 control */
1027 #define LOONGARCH_CSR_IB2ASID 0x3a3 /* inst breakpoint 2 asid */
1029 #define LOONGARCH_CSR_IB3ADDR 0x3a8 /* inst breakpoint 3 address */
1030 #define LOONGARCH_CSR_IB3MASK 0x3a9 /* breakpoint 3 mask */
1031 #define LOONGARCH_CSR_IB3CTL 0x3aa /* inst breakpoint 3 control */
1032 #define LOONGARCH_CSR_IB3ASID 0x3ab /* inst breakpoint 3 asid */
1034 #define LOONGARCH_CSR_IB4ADDR 0x3b0 /* inst breakpoint 4 address */
1035 #define LOONGARCH_CSR_IB4MASK 0x3b1 /* inst breakpoint 4 mask */
1036 #define LOONGARCH_CSR_IB4CTL 0x3b2 /* inst breakpoint 4 control */
1037 #define LOONGARCH_CSR_IB4ASID 0x3b3 /* inst breakpoint 4 asid */
1039 #define LOONGARCH_CSR_IB5ADDR 0x3b8 /* inst breakpoint 5 address */
1040 #define LOONGARCH_CSR_IB5MASK 0x3b9 /* inst breakpoint 5 mask */
1041 #define LOONGARCH_CSR_IB5CTL 0x3ba /* inst breakpoint 5 control */
1042 #define LOONGARCH_CSR_IB5ASID 0x3bb /* inst breakpoint 5 asid */
1044 #define LOONGARCH_CSR_IB6ADDR 0x3c0 /* inst breakpoint 6 address */
1045 #define LOONGARCH_CSR_IB6MASK 0x3c1 /* inst breakpoint 6 mask */
1046 #define LOONGARCH_CSR_IB6CTL 0x3c2 /* inst breakpoint 6 control */
1047 #define LOONGARCH_CSR_IB6ASID 0x3c3 /* inst breakpoint 6 asid */
1049 #define LOONGARCH_CSR_IB7ADDR 0x3c8 /* inst breakpoint 7 address */
1050 #define LOONGARCH_CSR_IB7MASK 0x3c9 /* inst breakpoint 7 mask */
1051 #define LOONGARCH_CSR_IB7CTL 0x3ca /* inst breakpoint 7 control */
1052 #define LOONGARCH_CSR_IB7ASID 0x3cb /* inst breakpoint 7 asid */
1054 #define LOONGARCH_CSR_DEBUG 0x500 /* debug config */
1055 #define LOONGARCH_CSR_DERA 0x501 /* debug era */
1056 #define LOONGARCH_CSR_DESAVE 0x502 /* debug save */
1061 #define ECFG0_IM 0x00001fff
1062 #define ECFGB_SIP0 0
1090 #define ESTATF_IP 0x00001fff
1092 #define LOONGARCH_IOCSR_FEATURES 0x8
1093 #define IOCSRF_TEMP BIT_ULL(0)
1105 #define LOONGARCH_IOCSR_VENDOR 0x10
1107 #define LOONGARCH_IOCSR_CPUNAME 0x20
1109 #define LOONGARCH_IOCSR_NODECNT 0x408
1111 #define LOONGARCH_IOCSR_MISC_FUNC 0x420
1115 #define LOONGARCH_IOCSR_CPUTEMP 0x428
1118 #define LOONGARCH_IOCSR_IPI_STATUS 0x1000
1119 #define LOONGARCH_IOCSR_IPI_EN 0x1004
1120 #define LOONGARCH_IOCSR_IPI_SET 0x1008
1121 #define LOONGARCH_IOCSR_IPI_CLEAR 0x100c
1122 #define LOONGARCH_IOCSR_MBUF0 0x1020
1123 #define LOONGARCH_IOCSR_MBUF1 0x1028
1124 #define LOONGARCH_IOCSR_MBUF2 0x1030
1125 #define LOONGARCH_IOCSR_MBUF3 0x1038
1127 #define LOONGARCH_IOCSR_IPI_SEND 0x1040
1128 #define IOCSR_IPI_SEND_IP_SHIFT 0
1132 #define LOONGARCH_IOCSR_MBUF_SEND 0x1048
1139 #define IOCSR_MBUF_SEND_H32_MASK 0xFFFFFFFF00000000ULL
1141 #define LOONGARCH_IOCSR_ANY_SEND 0x1158
1146 #define IOCSR_ANY_SEND_H32_MASK 0xFFFFFFFF00000000ULL
1149 #define LOONGARCH_IOCSR_TIMER_CFG 0x1060
1150 #define LOONGARCH_IOCSR_TIMER_TICK 0x1070
1154 #define IOCSR_TIMER_MASK 0x0ffffffffffffULL
1155 #define IOCSR_TIMER_INITVAL_RST (_ULCAST_(0xffff) << 48)
1157 #define LOONGARCH_IOCSR_EXTIOI_NODEMAP_BASE 0x14a0
1158 #define LOONGARCH_IOCSR_EXTIOI_IPMAP_BASE 0x14c0
1159 #define LOONGARCH_IOCSR_EXTIOI_EN_BASE 0x1600
1160 #define LOONGARCH_IOCSR_EXTIOI_BOUNCE_BASE 0x1680
1161 #define LOONGARCH_IOCSR_EXTIOI_ISR_BASE 0x1800
1162 #define LOONGARCH_IOCSR_EXTIOI_ROUTE_BASE 0x1c00
1169 int rID = 0; in drdtime()
1170 u64 val = 0; in drdtime()
1173 "rdtime.d %0, %1 \n\t" in drdtime()
1188 uint64_t val = 0; in csr_any_send()
1331 #define ENTRYLO_V (_ULCAST_(1) << 0)
1342 #define PS_4K 0x0000000c
1343 #define PS_8K 0x0000000d
1344 #define PS_16K 0x0000000e
1345 #define PS_32K 0x0000000f
1346 #define PS_64K 0x00000010
1347 #define PS_128K 0x00000011
1348 #define PS_256K 0x00000012
1349 #define PS_512K 0x00000013
1350 #define PS_1M 0x00000014
1351 #define PS_2M 0x00000015
1352 #define PS_4M 0x00000016
1353 #define PS_8M 0x00000017
1354 #define PS_16M 0x00000018
1355 #define PS_32M 0x00000019
1356 #define PS_64M 0x0000001a
1357 #define PS_128M 0x0000001b
1358 #define PS_256M 0x0000001c
1359 #define PS_512M 0x0000001d
1360 #define PS_1G 0x0000001e
1385 #define EXCCODE_RSV 0 /* Reserved */
1394 #define EXSUBCODE_ADEF 0 /* Fetch Instruction */
1406 #define EXCSUBCODE_FPE 0 /* Floating Point Exception */
1414 #define EXCSUBCODE_GCSC 0 /* Software caused */
1443 #define FPU_CSR_RSVD 0xe0e0fce0
1450 #define FPU_CSR_ALL_X 0x1f000000
1451 #define FPU_CSR_INV_X 0x10000000
1452 #define FPU_CSR_DIV_X 0x08000000
1453 #define FPU_CSR_OVF_X 0x04000000
1454 #define FPU_CSR_UDF_X 0x02000000
1455 #define FPU_CSR_INE_X 0x01000000
1457 #define FPU_CSR_ALL_S 0x001f0000
1458 #define FPU_CSR_INV_S 0x00100000
1459 #define FPU_CSR_DIV_S 0x00080000
1460 #define FPU_CSR_OVF_S 0x00040000
1461 #define FPU_CSR_UDF_S 0x00020000
1462 #define FPU_CSR_INE_S 0x00010000
1464 #define FPU_CSR_ALL_E 0x0000001f
1465 #define FPU_CSR_INV_E 0x00000010
1466 #define FPU_CSR_DIV_E 0x00000008
1467 #define FPU_CSR_OVF_E 0x00000004
1468 #define FPU_CSR_UDF_E 0x00000002
1469 #define FPU_CSR_INE_E 0x00000001
1472 #define FPU_CSR_RM 0x300
1473 #define FPU_CSR_RN 0x000 /* nearest */
1474 #define FPU_CSR_RZ 0x100 /* towards zero */
1475 #define FPU_CSR_RU 0x200 /* towards +Infinity */
1476 #define FPU_CSR_RD 0x300 /* towards -Infinity */
1483 " movfcsr2gr %0, "__stringify(source)" \n" \
1491 " movgr2fcsr %0, "__stringify(dest)" \n" \
1493 } while (0)