Lines Matching full:src0
33 #define src0 r2 macro
98 add src0=0,in1
146 add src1=8,src0 // 2nd src pointer
157 EX(.ex_handler, (p16) ld8 r34=[src0],16)
162 EX(.ex_handler, (p16) ld8 r32=[src0],16)
170 EX(.ex_handler, (p6) ld8 t1=[src0])
181 add src0=src0,r21 // setting up src pointer
194 mov src_pre_mem = src0
200 add src_pre_l2 = 8*8, src0
203 add src0 = 8, src_pre_mem // first t1 src
223 EX(.ex_handler, (p[D]) ld8 t2 = [src0], 3*8) // M0
233 EX(.ex_handler, (p[D]) ld8 t5 = [src0], 8)
238 EX(.ex_handler, (p[D]) ld8 t6 = [src0], 3*8)
243 EX(.ex_handler, (p[D]) ld8 t9 = [src0], 3*8)
248 EX(.ex_handler, (p[D]) ld8 t12 = [src0], 8)
253 EX(.ex_handler, (p[D]) ld8 t13 = [src0], 4*8)
258 EX(.ex_handler, (p[C]) ld8 t1 = [src0], 8)
266 add src0=-8,src0
293 mov saved_in1=src0
300 and r30=7,src0 // source alignment
306 add src_pre_mem=0,src0 // prefetch src pointer
308 and src0=-8,src0 // 1st src pointer
319 shladd src1=r22,3,src0 // 2nd src pointer
324 EX(.ex_handler, (p9) ld8 r33=[src0],8) // loop primer
356 add src0=8,src0
372 (p8) add src0=saved_in1,blocksize
403 add src0=src1,r30 // forward by src alignment
412 add src1=1,src0 // second src pointer
416 EX(.ex_handler_short, (p8) ld1 t1=[src0],2)
425 EX(.ex_handler_short, (p12) ld1 t3=[src0],2)
439 EX(.ex_handler_short, (p6) ld1 t5=[src0],2)
448 EX(.ex_handler_short, (p10) ld1 t7=[src0],2)
461 * src0 - source even index
472 EX(.ex_handler_short, (p6) ld1 t1=[src0],2)
477 EK(.ex_handler_short, (p8) ld1 t3=[src0],2)
483 EK(.ex_handler_short, (p10) ld1 t5=[src0],2)
488 EK(.ex_handler_short, (p12) ld1 t7=[src0],2)
497 add src0=in1,r30
505 EX(.ex_handler, (p16) ld8 r32=[src0],8); /* 1 */ \
544 * faulting address is calculated as page_round_down(max(src0, src1)).
565 add src0=8,src0
578 (p10) add src0=8,saved_in1
579 (p11) mov src0=saved_in1
586 // always ahead of src0/dst0.
596 cmp.ltu p10,p11=src0,src1
601 (p11) mov src1 = src0 // pick the larger of the two
609 (p7) cmp.le p14,p0=src0,saved_in1 // no progress has been made on load