Lines Matching +full:36 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0
3 * Instruction-patching support.
5 * Copyright (C) 2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
19 * The 64-bit value in a "movl reg=value" is scattered between the two words of the bundle
32 u64 *p = (u64 *) (insn_addr & -16); /* mask out slot number */ in get_imm64()
40 ((p[1] & 0x000007f000000000UL) >> 36); /*G*/ in get_imm64()
47 u64 m0, m1, v0, v1, b0, b1, *b = (u64 *) (insn_addr & -16); in ia64_patch()
48 # define insn_mask ((1UL << 41) - 1) in ia64_patch()
52 shift = 5 + 41 * (insn_addr % 16); /* 5 bits of template, then 3 x 41-bit instructions */ in ia64_patch()
54 m1 = mask << (shift - 64); in ia64_patch()
55 v1 = val << (shift - 64); in ia64_patch()
57 m0 = mask << shift; m1 = mask >> (64 - shift); in ia64_patch()
58 v0 = val << shift; v1 = val >> (64 - shift); in ia64_patch()
68 or slot 2 for a long (2-slot) instruction, occupying slots 1 in ia64_patch_imm64()
70 insn_addr &= -16UL; in ia64_patch_imm64()
72 0x01fffefe000UL, ( ((val & 0x8000000000000000UL) >> 27) /* bit 63 -> 36 */ in ia64_patch_imm64()
73 | ((val & 0x0000000000200000UL) << 0) /* bit 21 -> 21 */ in ia64_patch_imm64()
74 | ((val & 0x00000000001f0000UL) << 6) /* bit 16 -> 22 */ in ia64_patch_imm64()
75 | ((val & 0x000000000000ff80UL) << 20) /* bit 7 -> 27 */ in ia64_patch_imm64()
76 | ((val & 0x000000000000007fUL) << 13) /* bit 0 -> 13 */)); in ia64_patch_imm64()
84 or slot 2 for a long (2-slot) instruction, occupying slots 1 in ia64_patch_imm60()
86 insn_addr &= -16UL; in ia64_patch_imm60()
88 0x011ffffe000UL, ( ((val & 0x0800000000000000UL) >> 23) /* bit 59 -> 36 */ in ia64_patch_imm60()
89 | ((val & 0x00000000000fffffUL) << 13) /* bit 0 -> 13 */)); in ia64_patch_imm60()
132 b = (u64 *)(ip & -16); in ia64_patch_rse()
149 need_workaround = (local_cpu_data->family == 0x1f && local_cpu_data->model == 0); in ia64_patch_mckinley_e9()
199 (u64) (fsys_bubble_down - (ip & -16)) / 16); in patch_brl_fsys_bubble_down()