102 #define A64_LSX(sf, Rt, Rn, Rs, type) \  argument
103 	aarch64_insn_gen_load_store_ex(Rt, Rn, Rs, A64_SIZE(sf), \
108 /* [Rn] = Rt; (atomic) Rs = [state] */
109 #define A64_STXR(sf, Rt, Rn, Rs) \  argument
110 	A64_LSX(sf, Rt, Rn, Rs, STORE_EX)
111 /* [Rn] = Rt (store release); (atomic) Rs = [state] */
112 #define A64_STLXR(sf, Rt, Rn, Rs) \  argument
113 	aarch64_insn_gen_load_store_ex(Rt, Rn, Rs, A64_SIZE(sf), \
122 #define A64_ST_OP(sf, Rn, Rs, op) \  argument
123 	aarch64_insn_gen_atomic_ld_op(A64_ZR, Rn, Rs, \
126 /* [Rn] <op>= Rs */
127 #define A64_STADD(sf, Rn, Rs) A64_ST_OP(sf, Rn, Rs, ADD)  argument
128 #define A64_STCLR(sf, Rn, Rs) A64_ST_OP(sf, Rn, Rs, CLR)  argument
129 #define A64_STEOR(sf, Rn, Rs) A64_ST_OP(sf, Rn, Rs, EOR)  argument
130 #define A64_STSET(sf, Rn, Rs) A64_ST_OP(sf, Rn, Rs, SET)  argument
132 #define A64_LD_OP_AL(sf, Rt, Rn, Rs, op) \  argument
133 	aarch64_insn_gen_atomic_ld_op(Rt, Rn, Rs, \
136 /* Rt = [Rn] (load acquire); [Rn] <op>= Rs (store release) */
137 #define A64_LDADDAL(sf, Rt, Rn, Rs) A64_LD_OP_AL(sf, Rt, Rn, Rs, ADD)  argument
138 #define A64_LDCLRAL(sf, Rt, Rn, Rs) A64_LD_OP_AL(sf, Rt, Rn, Rs, CLR)  argument
139 #define A64_LDEORAL(sf, Rt, Rn, Rs) A64_LD_OP_AL(sf, Rt, Rn, Rs, EOR)  argument
140 #define A64_LDSETAL(sf, Rt, Rn, Rs) A64_LD_OP_AL(sf, Rt, Rn, Rs, SET)  argument
141 /* Rt = [Rn] (load acquire); [Rn] = Rs (store release) */
142 #define A64_SWPAL(sf, Rt, Rn, Rs) A64_LD_OP_AL(sf, Rt, Rn, Rs, SWP)  argument
143 /* Rs = CAS(Rn, Rs, Rt) (load acquire & store release) */
144 #define A64_CASAL(sf, Rt, Rn, Rs) \  argument
145 	aarch64_insn_gen_cas(Rt, Rn, Rs, A64_SIZE(sf), \