84 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
316 static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,  in set_oslsr_el1()  argument
323 	if ((val ^ rd->val) & ~SYS_OSLSR_OSLK)  in set_oslsr_el1()
326 	__vcpu_sys_reg(vcpu, rd->reg) = val;  in set_oslsr_el1()
396 		       const struct sys_reg_desc *rd,  in reg_to_dbg()  argument
401 	get_access_mask(rd, &mask, &shift);  in reg_to_dbg()
413 		       const struct sys_reg_desc *rd,  in dbg_to_reg()  argument
418 	get_access_mask(rd, &mask, &shift);  in dbg_to_reg()
424 		     const struct sys_reg_desc *rd)  in trap_bvr()  argument
426 	u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];  in trap_bvr()
429 		reg_to_dbg(vcpu, p, rd, dbg_reg);  in trap_bvr()
431 		dbg_to_reg(vcpu, p, rd, dbg_reg);  in trap_bvr()
433 	trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);  in trap_bvr()
438 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,  in set_bvr()  argument
441 	vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = val;  in set_bvr()
445 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,  in get_bvr()  argument
448 	*val = vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];  in get_bvr()
453 		      const struct sys_reg_desc *rd)  in reset_bvr()  argument
455 	vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val;  in reset_bvr()
460 		     const struct sys_reg_desc *rd)  in trap_bcr()  argument
462 	u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];  in trap_bcr()
465 		reg_to_dbg(vcpu, p, rd, dbg_reg);  in trap_bcr()
467 		dbg_to_reg(vcpu, p, rd, dbg_reg);  in trap_bcr()
469 	trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);  in trap_bcr()
474 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,  in set_bcr()  argument
477 	vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = val;  in set_bcr()
481 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,  in get_bcr()  argument
484 	*val = vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];  in get_bcr()
489 		      const struct sys_reg_desc *rd)  in reset_bcr()  argument
491 	vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val;  in reset_bcr()
496 		     const struct sys_reg_desc *rd)  in trap_wvr()  argument
498 	u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];  in trap_wvr()
501 		reg_to_dbg(vcpu, p, rd, dbg_reg);  in trap_wvr()
503 		dbg_to_reg(vcpu, p, rd, dbg_reg);  in trap_wvr()
505 	trace_trap_reg(__func__, rd->CRm, p->is_write,  in trap_wvr()
506 		vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]);  in trap_wvr()
511 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,  in set_wvr()  argument
514 	vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = val;  in set_wvr()
518 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,  in get_wvr()  argument
521 	*val = vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];  in get_wvr()
526 		      const struct sys_reg_desc *rd)  in reset_wvr()  argument
528 	vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val;  in reset_wvr()
533 		     const struct sys_reg_desc *rd)  in trap_wcr()  argument
535 	u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];  in trap_wcr()
538 		reg_to_dbg(vcpu, p, rd, dbg_reg);  in trap_wcr()
540 		dbg_to_reg(vcpu, p, rd, dbg_reg);  in trap_wcr()
542 	trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);  in trap_wcr()
547 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,  in set_wcr()  argument
550 	vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = val;  in set_wcr()
554 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,  in get_wcr()  argument
557 	*val = vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];  in get_wcr()
562 		      const struct sys_reg_desc *rd)  in reset_wcr()  argument
564 	vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val;  in reset_wcr()
802 		idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);  in access_pmu_evcntr()
836 		idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);  in access_pmu_evtyper()
1010 			const struct sys_reg_desc *rd)  in ptrauth_visibility()  argument
1182 				   const struct sys_reg_desc *rd)  in sve_visibility()  argument
1191 			       const struct sys_reg_desc *rd,  in set_id_aa64pfr0_el1()  argument
1213 	val ^= read_id_reg(vcpu, rd);  in set_id_aa64pfr0_el1()
1232 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,  in get_id_reg()  argument
1235 	*val = read_id_reg(vcpu, rd);  in get_id_reg()
1239 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,  in set_id_reg()  argument
1243 	if (val != read_id_reg(vcpu, rd))  in set_id_reg()
1249 static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,  in get_raz_reg()  argument
1256 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,  in set_wi_reg()  argument
1318 		p->regval &= ~GENMASK(27, 3);  in access_ccsidr()
1323 				   const struct sys_reg_desc *rd)  in mte_visibility()  argument
1359  * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
1363 	Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2),	\
1404 	DBG_BCR_BVR_WCR_WVR_EL1(3),
1463 	/* CRm=3 */
1467 	ID_UNALLOCATED(3,3),
1471 	ID_UNALLOCATED(3,7),
1479 	ID_UNALLOCATED(4,3),
1489 	ID_UNALLOCATED(5,3),
1499 	ID_UNALLOCATED(6,3),
1509 	ID_UNALLOCATED(7,3),
1666 	AMU_AMEVCNTR0_EL0(3),
1682 	AMU_AMEVTYPER0_EL0(3),
1698 	AMU_AMEVCNTR1_EL0(3),
1714 	AMU_AMEVTYPER1_EL0(3),
1736 	PMU_PMEVCNTR_EL0(3),
1768 	PMU_PMEVTYPER_EL0(3),
1870 	{ Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
1872 	{ Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
1873 	DBG_BCR_BVR_WCR_WVR(3),
1903 	DBGBXVR(3),
1905 	{ Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
1955 	  (0b1000 | (((n) >> 3) & 0x3)), ((n) & 0x7)),			\
1961 	  (0b1100 | (((n) >> 3) & 0x3)), ((n) & 0x7)),			\
1974 	{ AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 },
1980 	{ AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 },
1981 	{ Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 },
2005 	{ CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 3), .access = access_pmovs },
2016 	{ CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 3), .access = access_pmovs },
2027 	{ AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 },
2029 	{ AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 },
2044 	PMU_PMEVCNTR(3),
2076 	PMU_PMEVTYPER(3),
2291 	params->Op0 = 3;  in kvm_esr_cp10_id_to_sys64()
2294 	params->CRm = 3;  in kvm_esr_cp10_id_to_sys64()
2361  * registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same.
2379 	params->Op0 = 3;  in kvm_emulate_cp15_id_reg()
2382 	 * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32.  in kvm_emulate_cp15_id_reg()
2386 	if (params->CRm > 3)  in kvm_emulate_cp15_id_reg()
2459 	return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011;  in is_imp_def_sys_reg()
2670 	/* Bottom bit is Instruction or Data bit.  Next 3 bits are level. */  in is_valid_cache()
2672 	ctype = (cache_levels >> (level * 3)) & 7;  in is_valid_cache()
2682 	case 3: /* Separate instruction and data caches */  in is_valid_cache()
2881 			    const struct sys_reg_desc *rd,  in walk_one_sys_reg()  argument
2889 	if (!(rd->reg || rd->get_user))  in walk_one_sys_reg()
2892 	if (sysreg_hidden(vcpu, rd))  in walk_one_sys_reg()
2895 	if (!copy_reg_to_user(rd, uind))  in walk_one_sys_reg()
2981 		if (((cache_levels >> (i*3)) & 7) == 0)  in kvm_sys_reg_table_init()
2984 	cache_levels &= (1 << (i*3))-1;  in kvm_sys_reg_table_init()