Lines Matching +full:last +full:- +full:level
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Low-level CPU initialisation
6 * Copyright (C) 1994-2002 Russell King
7 * Copyright (C) 2003-2012 ARM Ltd.
21 #include <asm/asm-offsets.h>
27 #include <asm/kernel-pgtable.h>
30 #include <asm/pgtable-hwdef.h>
38 #include "efi-header.S"
46 * ---------------------------
49 * MMU = off, D-cache = off, I-cache = on or off,
52 * Note that the callee-saved registers are used for storing variables
58 * DO NOT MODIFY. Image header expected by Linux boot-loaders.
62 .quad 0 // Image load offset from start of RAM, little-endian
63 le64sym _kernel_size_le // Effective size of kernel image, little-endian
64 le64sym _kernel_flags_le // Informative flags, little-endian
141 * Macro to populate page table entries, these entries can be pointers to the next level
142 * or last level entries pointing to physical memory.
147 * eindex: end index to write - [index, eindex] written to
160 add \rtbl, \rtbl, \inc // rtbl = pa next level
168 * were needed in the previous page table level then the next page table level is assumed
172 * vend: virtual address of end of range - we map [vstart, vend]
177 * count: On entry: how many extra entries were required in previous level, scales
179 * On exit: returns how many extra entries required for next page table level
192 * Map memory for specified virtual address range. Each level of page table needed supports
193 * multiple entries. If a level requires n entries the next page table level is assumed to be
197 * rtbl: address to be used for first level page table entry (typically tbl + PAGE_SIZE)
199 * vend: virtual address of end of range - we map [vstart, vend - 1]
200 * flags: flags to use to map last level entries
201 * phys: physical address corresponding to vstart - physical memory is contiguous
204 * If extra_shift is set, an extra level will be populated if the end address does
207 * Temporaries: istart, iend, tmp, count, sv - these need to be different registers
217 tst \vend, #~((1 << (\extra_shift)) - 1)
219 compute_indices \vstart, \vend, #\extra_shift, #(PAGE_SHIFT - 3), \istart, \iend, \count
231 compute_indices \vstart, \vend, #PUD_SHIFT, #(PAGE_SHIFT - 3), \istart, \iend, \count
238 compute_indices \vstart, \vend, #SWAPPER_TABLE_SHIFT, #(PAGE_SHIFT - 3), \istart, \iend, \count
244 compute_indices \vstart, \vend, #SWAPPER_BLOCK_SHIFT, #(PAGE_SHIFT - 3), \istart, \iend, \count
245 bic \rtbl, \phys, #SWAPPER_BLOCK_SIZE - 1
254 * x0: last level table address (returned in first argument to map_memory)
260 * x6: order of the last level mappings
265 // Get the index offset for the start of the last level table
267 bfi x1, xzr, #0, #PAGE_SHIFT - 3
269 // Derive the start and end indexes into the last level table
277 lsl x6, x1, x6 // block size at this level
293 * - 39 <= VA_BITS < 48, and the ID map needs up to 48 VA bits to cover
295 * level of translation on the fly for the ID map only. (This case
296 * also covers 42-bit VA/52-bit PA on 64k pages).
298 * - VA_BITS == 48, and the ID map needs more than 48 VA bits. This can
300 * the root level table rather than add a level. Note that we can
304 * - Combinations that would require two additional levels of
306 * VA_BITS==39/4k pages with 5-level paging, where the input address
310 #define IDMAP_PGD_ORDER (VA_BITS - PGDIR_SHIFT)
311 #define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3)
314 * If VA_BITS < 48, we have to configure an additional table level.
318 * translation level to be configured.
324 #define IDMAP_PGD_ORDER (PHYS_MASK_SHIFT - PGDIR_SHIFT)
328 * translation level, but the top-level table has more entries.
342 bic x4, x2, #SWAPPER_BLOCK_SIZE - 1
350 bic x2, x22, #SWAPPER_BLOCK_SIZE - 1
353 bic x4, x21, #SWAPPER_BLOCK_SIZE - 1
359 * Since the page tables have been populated with non-cacheable
379 sub x6, x6, x3 // _end - _text
383 map_memory x0, x1, x5, x6, x7, x3, (VA_BITS - PGDIR_SHIFT), x10, x11, x12, x13, x14
390 * Initialize CPU registers with task-specific and cpu-specific context.
392 * Create a final frame record at task_pt_regs(current)->stackframe, so
428 stp x29, x30, [sp, #-16]!
633 * - Corrupts tmp1, tmp2
634 * - Writes 'status' to __early_cpu_boot_status and makes sure
719 ldr x14, [x9, #-8]
738 * the last address entry.
745 * Excluding the least significant bit in the bitmap, each non-zero
751 * a single bitmap can encode up to 63 relocations in a 64-bit object.
802 and x23, x23, MIN_KIMG_ALIGN - 1
809 and x24, x0, #SZ_2M - 1 // capture memstart offset seed
810 bic x0, x0, #SZ_2M - 1