Lines Matching +full:0 +full:x29
33 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29
41 .if \el == 0
65 tbnz x0, #THREAD_SHIFT, 0f
70 0:
127 nop // Patched to SMC/HVC #0
203 stp x0, x1, [sp, #16 * 0]
217 stp x28, x29, [sp, #16 * 14]
219 .if \el == 0
279 .endif /* \el == 0 */
289 .if \el == 0
292 stp x29, x22, [sp, #S_STACKFRAME]
294 add x29, sp, #S_STACKFRAME
305 .if \el == 0
331 .if \el != 0
355 .if \el == 0
364 mrs x29, contextidr_el1
365 msr contextidr_el1, x29
400 apply_ssbd 0, x0, x1
405 ldp x0, x1, [sp, #16 * 0]
419 ldp x28, x29, [sp, #16 * 14]
421 .if \el == 0
429 msr far_el1, x29
430 tramp_alias x30, tramp_exit_native, x29
433 tramp_alias x30, tramp_exit_compat, x29
475 1: and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit
513 kernel_ventry 0, t, 64, sync // Synchronous 64-bit EL0
514 kernel_ventry 0, t, 64, irq // IRQ 64-bit EL0
515 kernel_ventry 0, t, 64, fiq // FIQ 64-bit EL0
516 kernel_ventry 0, t, 64, error // Error 64-bit EL0
518 kernel_ventry 0, t, 32, sync // Synchronous 32-bit EL0
519 kernel_ventry 0, t, 32, irq // IRQ 32-bit EL0
520 kernel_ventry 0, t, 32, fiq // FIQ 32-bit EL0
521 kernel_ventry 0, t, 32, error // Error 32-bit EL0
560 .if \el == 0
581 entry_handler 0, t, 64, sync
582 entry_handler 0, t, 64, irq
583 entry_handler 0, t, 64, fiq
584 entry_handler 0, t, 64, error
586 entry_handler 0, t, 32, sync
587 entry_handler 0, t, 32, irq
588 entry_handler 0, t, 32, fiq
589 entry_handler 0, t, 32, error
601 kernel_exit 0
656 * instruction to load the upper 16 bits (which must be 0xFFFF).
664 #define BHB_MITIGATION_NONE 0
727 get_this_cpu_offset x29
728 ldr x30, [x30, x29]
732 tramp_unmap_kernel x29
734 mrs x29, far_el1
743 .space 0x400
797 tramp_ventry .Lvector_start\@, 64, 0, \bhb
800 tramp_ventry .Lvector_start\@, 32, 0, \bhb
834 stp x29, x9, [x8], #16
842 ldp x29, x9, [x8], #16
880 stp x29, x30, [sp, #-16]!
881 mov x29, sp
895 mov sp, x29
896 ldp x29, x30, [sp], #16
913 smc #0
915 99: hvc #0
992 stp x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14]
1035 and x0, x3, #0xc
1038 csel x29, x29, xzr, eq // fp, or zero
1041 stp x29, x4, [sp, #-16]!
1042 mov x29, sp
1051 ldp x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14]