Lines Matching +full:12 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
16 #include <asm/gpr-num.h>
22 * [20-19] : Op0
23 * [18-16] : Op1
24 * [15-12] : CRn
25 * [11-8] : CRm
26 * [7-5] : Op2
32 #define CRn_shift 12
83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
123 #include "asm/sysreg-defs.h"
145 #define SYS_OSLAR_OSLK BIT(0)
148 #define SYS_OSLSR_OSLM_MASK (BIT(3) | BIT(0))
150 #define SYS_OSLSR_OSLM_IMPLEMENTED BIT(3)
151 #define SYS_OSLSR_OSLK BIT(1)
236 #define SYS_PAR_EL1_F BIT(0)
250 #define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12
350 #define TRBLIMITR_LIMIT_SHIFT 12
351 #define TRBLIMITR_NVM BIT(5)
356 #define TRBLIMITR_ENABLE BIT(0)
360 #define TRBBASER_BASE_SHIFT 12
363 #define TRBSR_IRQ BIT(22)
364 #define TRBSR_TRG BIT(21)
365 #define TRBSR_WRAP BIT(20)
366 #define TRBSR_ABORT BIT(18)
367 #define TRBSR_STOP BIT(17)
382 #define TRBIDR_FLAG BIT(5)
383 #define TRBIDR_PROG BIT(4)
395 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
396 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
398 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
399 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
400 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
401 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
402 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
407 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
412 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
413 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3)
414 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
415 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6)
416 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7)
417 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
418 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
419 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2)
420 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
421 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
422 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
423 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
424 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
434 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
435 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
436 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
437 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
438 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
439 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5)
440 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
441 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
470 * n: 0-15
476 * n: 0-15
481 #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
530 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
531 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
537 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
543 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
544 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
545 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
546 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
547 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
548 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
549 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
550 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
552 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
562 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
585 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
595 #define SCTLR_ELx_ENTP2 (BIT(60))
596 #define SCTLR_ELx_DSSBS (BIT(44))
597 #define SCTLR_ELx_ATA (BIT(43))
601 #define SCTLR_ELx_ITFSB (BIT(37))
602 #define SCTLR_ELx_ENIA (BIT(SCTLR_ELx_ENIA_SHIFT))
603 #define SCTLR_ELx_ENIB (BIT(30))
604 #define SCTLR_ELx_LSMAOE (BIT(29))
605 #define SCTLR_ELx_nTLSMD (BIT(28))
606 #define SCTLR_ELx_ENDA (BIT(27))
607 #define SCTLR_ELx_EE (BIT(25))
608 #define SCTLR_ELx_EIS (BIT(22))
609 #define SCTLR_ELx_IESB (BIT(21))
610 #define SCTLR_ELx_TSCXT (BIT(20))
611 #define SCTLR_ELx_WXN (BIT(19))
612 #define SCTLR_ELx_ENDB (BIT(13))
613 #define SCTLR_ELx_I (BIT(12))
614 #define SCTLR_ELx_EOS (BIT(11))
615 #define SCTLR_ELx_SA (BIT(3))
616 #define SCTLR_ELx_C (BIT(2))
617 #define SCTLR_ELx_A (BIT(1))
618 #define SCTLR_ELx_M (BIT(0))
621 #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \
622 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \
623 (BIT(29)))
706 #define ID_ISAR4_SMC_SHIFT 12
716 #define ID_ISAR0_CMPBRANCH_SHIFT 12
723 #define ID_ISAR5_SHA2_SHIFT 12
731 #define ID_ISAR6_SB_SHIFT 12
740 #define ID_MMFR0_SHARELVL_SHIFT 12
749 #define ID_MMFR4_CNP_SHIFT 12
758 #define ID_PFR0_STATE3_SHIFT 12
766 #define ID_DFR0_COPTRC_SHIFT 12
778 #define MVFR0_FPTRAP_SHIFT 12
787 #define MVFR1_SIMDINT_SHIFT 12
796 #define ID_PFR1_VIRTUALIZATION_SHIFT 12
821 #define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */
822 #define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */
824 #define CPACR_EL1_SMEN_EL1EN (BIT(24)) /* enable EL1 access */
825 #define CPACR_EL1_SMEN_EL0EN (BIT(25)) /* enable EL0 access, if EL1EN set */
827 #define CPACR_EL1_ZEN_EL1EN (BIT(16)) /* enable EL1 access */
828 #define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */
831 #define SYS_GCR_EL1_RRND (BIT(16))
837 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
858 /* TFSR{,E0}_EL1 bit definitions */
865 #define SYS_MPIDR_SAFE_VAL (BIT(31))
872 #define TRFCR_EL2_CX BIT(3)
873 #define TRFCR_ELx_ExTRE BIT(1)
874 #define TRFCR_ELx_E0TRE BIT(0)
877 /* ICH_MISR_EL2 bit definitions */
881 /* ICH_LR*_EL2 bit definitions */
882 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
895 /* ICH_HCR_EL2 bit definitions */
901 #define ICH_HCR_TALL1 (1 << 12)
906 /* ICH_VMCR_EL2 bit definitions */
926 /* ICH_VTR_EL2 bit definitions */
938 /* HFG[WR]TR_EL2 bit definitions */
947 #define ARM64_FEATURE_MASK(x) (GENMASK_ULL(x##_SHIFT + ARM64_FEATURE_FIELD_BITS - 1, x##_SHIFT))
1031 * set mask are set. Other bits are left as-is.