Lines Matching +full:0 +full:- +full:3

1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
16 #include <asm/gpr-num.h>
22 * [20-19] : Op0
23 * [18-16] : Op1
24 * [15-12] : CRn
25 * [11-8] : CRm
26 * [7-5] : Op2
29 #define Op0_mask 0x3
31 #define Op1_mask 0x7
33 #define CRn_mask 0xf
35 #define CRm_mask 0xf
37 #define Op2_mask 0x7
67 #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \
68 (((x) << 8) & 0x00ff0000) | \
69 (((x) >> 8) & 0x0000ff00) | \
70 (((x) >> 24) & 0x000000ff))
83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
86 * Op0 = 0, CRn = 4
89 * Rt = 0x1f
94 #define PSTATE_PAN pstate_field(0, 4)
95 #define PSTATE_UAO pstate_field(0, 3)
96 #define PSTATE_SSBS pstate_field(3, 1)
97 #define PSTATE_TCO pstate_field(3, 4)
99 #define SET_PSTATE_PAN(x) __emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift))
100 #define SET_PSTATE_UAO(x) __emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift))
101 #define SET_PSTATE_SSBS(x) __emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift))
102 #define SET_PSTATE_TCO(x) __emit_inst(0xd500401f | PSTATE_TCO | ((!!x) << PSTATE_Imm_shift))
109 __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
111 #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31)
113 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)
114 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
115 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
123 #include "asm/sysreg-defs.h"
129 #define SYS_SVCR_SMSTOP_SM_EL0 sys_reg(0, 3, 4, 2, 3)
130 #define SYS_SVCR_SMSTART_SM_EL0 sys_reg(0, 3, 4, 3, 3)
131 #define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3)
133 #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2)
134 #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0)
135 #define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2)
136 #define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2)
137 #define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2)
138 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4)
139 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5)
140 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6)
141 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7)
142 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0)
144 #define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4)
145 #define SYS_OSLAR_OSLK BIT(0)
147 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4)
148 #define SYS_OSLSR_OSLM_MASK (BIT(3) | BIT(0))
149 #define SYS_OSLSR_OSLM_NI 0
150 #define SYS_OSLSR_OSLM_IMPLEMENTED BIT(3)
153 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4)
154 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4)
155 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
156 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
157 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6)
158 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0)
159 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0)
160 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
161 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
162 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
164 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
165 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
166 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
168 #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0)
169 #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1)
170 #define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4)
171 #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
172 #define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3, 5)
173 #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
174 #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4)
175 #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5)
176 #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6)
177 #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7)
178 #define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6)
179 #define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6)
181 #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0)
182 #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1)
183 #define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2)
184 #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3)
185 #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4)
186 #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5)
187 #define SYS_ID_ISAR6_EL1 sys_reg(3, 0, 0, 2, 7)
189 #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0)
190 #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1)
191 #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2)
193 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
194 #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
195 #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
197 #define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
199 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
201 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
202 #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1)
203 #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2)
204 #define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3)
206 #define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0)
207 #define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1)
208 #define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2)
209 #define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3)
211 #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0)
212 #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1)
214 #define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0)
215 #define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1)
217 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
219 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
220 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1)
221 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0)
223 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0)
224 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1)
225 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0)
226 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1)
227 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2)
228 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3)
229 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0)
230 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1)
231 #define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0)
232 #define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1)
234 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
236 #define SYS_PAR_EL1_F BIT(0)
241 #define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7)
242 #define SYS_PMSIDR_EL1_FE_SHIFT 0
245 #define SYS_PMSIDR_EL1_ARCHINST_SHIFT 3
249 #define SYS_PMSIDR_EL1_INTERVAL_MASK 0xfUL
251 #define SYS_PMSIDR_EL1_MAXSIZE_MASK 0xfUL
253 #define SYS_PMSIDR_EL1_COUNTSIZE_MASK 0xfUL
255 #define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7)
256 #define SYS_PMBIDR_EL1_ALIGN_SHIFT 0
257 #define SYS_PMBIDR_EL1_ALIGN_MASK 0xfU
262 #define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0)
263 #define SYS_PMSCR_EL1_E0SPE_SHIFT 0
265 #define SYS_PMSCR_EL1_CX_SHIFT 3
270 #define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0)
271 #define SYS_PMSCR_EL2_E0HSPE_SHIFT 0
273 #define SYS_PMSCR_EL2_CX_SHIFT 3
278 #define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2)
280 #define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3)
281 #define SYS_PMSIRR_EL1_RND_SHIFT 0
283 #define SYS_PMSIRR_EL1_INTERVAL_MASK 0xffffffUL
286 #define SYS_PMSNEVFR_EL1 sys_reg(3, 0, 9, 9, 1)
288 #define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4)
289 #define SYS_PMSFCR_EL1_FE_SHIFT 0
296 #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5)
299 BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0))
303 #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6)
304 #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0
307 #define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0)
308 #define SYS_PMBLIMITR_EL1_E_SHIFT 0
310 #define SYS_PMBLIMITR_EL1_FM_MASK 0x3UL
311 #define SYS_PMBLIMITR_EL1_FM_STOP_IRQ (0 << SYS_PMBLIMITR_EL1_FM_SHIFT)
313 #define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1)
316 #define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3)
322 #define SYS_PMBSR_EL1_EC_MASK 0x3fUL
324 #define SYS_PMBSR_EL1_EC_BUF (0x0UL << SYS_PMBSR_EL1_EC_SHIFT)
325 #define SYS_PMBSR_EL1_EC_FAULT_S1 (0x24UL << SYS_PMBSR_EL1_EC_SHIFT)
326 #define SYS_PMBSR_EL1_EC_FAULT_S2 (0x25UL << SYS_PMBSR_EL1_EC_SHIFT)
328 #define SYS_PMBSR_EL1_FAULT_FSC_SHIFT 0
329 #define SYS_PMBSR_EL1_FAULT_FSC_MASK 0x3fUL
331 #define SYS_PMBSR_EL1_BUF_BSC_SHIFT 0
332 #define SYS_PMBSR_EL1_BUF_BSC_MASK 0x3fUL
334 #define SYS_PMBSR_EL1_BUF_BSC_FULL (0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT)
341 #define SYS_TRBLIMITR_EL1 sys_reg(3, 0, 9, 11, 0)
342 #define SYS_TRBPTR_EL1 sys_reg(3, 0, 9, 11, 1)
343 #define SYS_TRBBASER_EL1 sys_reg(3, 0, 9, 11, 2)
344 #define SYS_TRBSR_EL1 sys_reg(3, 0, 9, 11, 3)
345 #define SYS_TRBMAR_EL1 sys_reg(3, 0, 9, 11, 4)
346 #define SYS_TRBTRG_EL1 sys_reg(3, 0, 9, 11, 6)
347 #define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7)
349 #define TRBLIMITR_LIMIT_MASK GENMASK_ULL(51, 0)
352 #define TRBLIMITR_TRIG_MODE_MASK GENMASK(1, 0)
353 #define TRBLIMITR_TRIG_MODE_SHIFT 3
354 #define TRBLIMITR_FILL_MODE_MASK GENMASK(1, 0)
356 #define TRBLIMITR_ENABLE BIT(0)
357 #define TRBPTR_PTR_MASK GENMASK_ULL(63, 0)
358 #define TRBPTR_PTR_SHIFT 0
359 #define TRBBASER_BASE_MASK GENMASK_ULL(51, 0)
361 #define TRBSR_EC_MASK GENMASK(5, 0)
368 #define TRBSR_MSS_MASK GENMASK(15, 0)
369 #define TRBSR_MSS_SHIFT 0
370 #define TRBSR_BSC_MASK GENMASK(5, 0)
371 #define TRBSR_BSC_SHIFT 0
372 #define TRBSR_FSC_MASK GENMASK(5, 0)
373 #define TRBSR_FSC_SHIFT 0
374 #define TRBMAR_SHARE_MASK GENMASK(1, 0)
376 #define TRBMAR_OUTER_MASK GENMASK(3, 0)
378 #define TRBMAR_INNER_MASK GENMASK(3, 0)
379 #define TRBMAR_INNER_SHIFT 0
380 #define TRBTRG_TRG_MASK GENMASK(31, 0)
381 #define TRBTRG_TRG_SHIFT 0
384 #define TRBIDR_ALIGN_MASK GENMASK(3, 0)
385 #define TRBIDR_ALIGN_SHIFT 0
387 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
388 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
390 #define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6)
392 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
393 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
395 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
396 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
398 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
399 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
400 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
401 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
402 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
403 #define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0)
406 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3)
407 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
408 #define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0)
411 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3)
412 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
413 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3)
414 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
415 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6)
416 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7)
417 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
418 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
419 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2)
420 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
421 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
422 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
423 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
424 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
426 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
428 #define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0, 0)
429 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
431 #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
432 #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1)
434 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
435 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
436 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
437 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
438 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
439 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5)
440 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
441 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
442 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
443 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
444 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2)
445 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
446 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
448 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2)
449 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3)
450 #define SYS_TPIDR2_EL0 sys_reg(3, 3, 13, 0, 5)
452 #define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7)
455 #define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2))
456 #define SYS_AMCR_EL0 SYS_AM_EL0(2, 0)
459 #define SYS_AMUSERENR_EL0 SYS_AM_EL0(2, 3)
462 #define SYS_AMCNTENCLR1_EL0 SYS_AM_EL0(3, 0)
463 #define SYS_AMCNTENSET1_EL0 SYS_AM_EL0(3, 1)
466 * Group 0 of activity monitors (architected):
468 * Counter: 11 011 1101 010:n<3> n<2:0>
469 * Type: 11 011 1101 011:n<3> n<2:0>
470 * n: 0-15
474 * Counter: 11 011 1101 110:n<3> n<2:0>
475 * Type: 11 011 1101 111:n<3> n<2:0>
476 * n: 0-15
479 #define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
480 #define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7)
481 #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
482 #define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
485 #define SYS_AMEVCNTR0_CORE_EL0 SYS_AMEVCNTR0_EL0(0)
488 #define SYS_AMEVCNTR0_MEM_STALL SYS_AMEVCNTR0_EL0(3)
490 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
492 #define SYS_CNTPCTSS_EL0 sys_reg(3, 3, 14, 0, 5)
493 #define SYS_CNTVCTSS_EL0 sys_reg(3, 3, 14, 0, 6)
495 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0)
496 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1)
497 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2)
499 #define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1)
500 #define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2)
502 #define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0)
503 #define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1)
504 #define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0)
506 #define __PMEV_op2(n) ((n) & 0x7)
507 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3))
508 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
509 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3))
510 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
512 #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7)
514 #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0)
515 #define SYS_HFGRTR_EL2 sys_reg(3, 4, 1, 1, 4)
516 #define SYS_HFGWTR_EL2 sys_reg(3, 4, 1, 1, 5)
517 #define SYS_HFGITR_EL2 sys_reg(3, 4, 1, 1, 6)
518 #define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
519 #define SYS_HDFGRTR_EL2 sys_reg(3, 4, 3, 1, 4)
520 #define SYS_HDFGWTR_EL2 sys_reg(3, 4, 3, 1, 5)
521 #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
522 #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
523 #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
524 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
525 #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0)
526 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
527 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
528 #define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0)
530 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
531 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
532 #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0)
535 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3)
537 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
538 #define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0)
541 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3)
543 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
544 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
545 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
546 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
547 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
548 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
549 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
550 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
552 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
553 #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0)
556 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3)
562 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
563 #define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0)
566 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3)
573 #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
574 #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
575 #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
576 #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2)
577 #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
578 #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
579 #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
580 #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
581 #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
582 #define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0)
583 #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
584 #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
585 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
586 #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
587 #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
588 #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
589 #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2)
590 #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0)
591 #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1)
592 #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2)
615 #define SCTLR_ELx_SA (BIT(3))
618 #define SCTLR_ELx_M (BIT(0))
628 #define ENDIAN_SET_EL2 0
643 #define ENDIAN_SET_EL1 0
660 #define MAIR_ATTR_DEVICE_nGnRnE UL(0x00)
661 #define MAIR_ATTR_DEVICE_nGnRE UL(0x04)
662 #define MAIR_ATTR_NORMAL_NC UL(0x44)
663 #define MAIR_ATTR_NORMAL_TAGGED UL(0xf0)
664 #define MAIR_ATTR_NORMAL UL(0xff)
665 #define MAIR_ATTR_MASK UL(0xff)
671 #define ID_AA64PFR0_EL1_ELx_64BIT_ONLY 0x1
672 #define ID_AA64PFR0_EL1_ELx_32BIT_64BIT 0x2
675 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN 0x0
676 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX 0x7
677 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN 0x0
678 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX 0x7
679 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN 0x1
680 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX 0xf
684 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT 0x0
685 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE 0x1
686 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN 0x2
687 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX 0x7
697 #define ID_DFR0_PERFMON_8_0 0x3
698 #define ID_DFR0_PERFMON_8_1 0x4
699 #define ID_DFR0_PERFMON_8_4 0x5
700 #define ID_DFR0_PERFMON_8_5 0x6
709 #define ID_ISAR4_UNPRIV_SHIFT 0
711 #define ID_DFR1_MTPMU_SHIFT 0
719 #define ID_ISAR0_SWAP_SHIFT 0
726 #define ID_ISAR5_SEVL_SHIFT 0
734 #define ID_ISAR6_JSCVT_SHIFT 0
743 #define ID_MMFR0_VMSA_SHIFT 0
752 #define ID_MMFR4_SPECSEI_SHIFT 0
754 #define ID_MMFR5_ETS_SHIFT 0
761 #define ID_PFR0_STATE0_SHIFT 0
769 #define ID_DFR0_COPDBG_SHIFT 0
772 #define ID_PFR2_CSV3_SHIFT 0
781 #define MVFR0_SIMD_SHIFT 0
790 #define MVFR1_FPFTZ_SHIFT 0
799 #define ID_PFR1_PROGMOD_SHIFT 0
819 #define MVFR2_SIMDMISC_SHIFT 0
832 #define SYS_GCR_EL1_EXCL_MASK 0xffffUL
837 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
839 #define __MTE_TAG_MIN (KASAN_TAG_MIN & 0xf)
840 #define __MTE_TAG_MAX (KASAN_TAG_MAX & 0xf)
850 #define SYS_RGSR_EL1_TAG_MASK 0xfUL
852 #define SYS_RGSR_EL1_SEED_MASK 0xffffUL
855 #define GMID_EL1_BS_SHIFT 0
859 #define SYS_TFSR_EL1_TF0_SHIFT 0
864 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
868 #define TRFCR_ELx_TS_MASK ((0x3UL) << TRFCR_ELx_TS_SHIFT)
869 #define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT)
870 #define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT)
871 #define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT)
872 #define TRFCR_EL2_CX BIT(3)
874 #define TRFCR_ELx_E0TRE BIT(0)
878 #define ICH_MISR_EOI (1 << 0)
882 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
887 #define ICH_LR_STATE (3ULL << 62)
891 #define ICH_LR_PHYS_ID_MASK (0x3ffULL << ICH_LR_PHYS_ID_SHIFT)
893 #define ICH_LR_PRIORITY_MASK (0xffULL << ICH_LR_PRIORITY_SHIFT)
896 #define ICH_HCR_EN (1 << 0)
898 #define ICH_HCR_NPIE (1 << 3)
904 #define ICH_HCR_EOIcount_MASK (0x1f << ICH_HCR_EOIcount_SHIFT)
909 #define ICH_VMCR_FIQ_EN_SHIFT 3
920 #define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT)
921 #define ICH_VMCR_ENG0_SHIFT 0
947 #define ARM64_FEATURE_MASK(x) (GENMASK_ULL(x##_SHIFT + ARM64_FEATURE_FIELD_BITS - 1, x##_SHIFT))
952 __emit_inst(0xd5200000|(\sreg)|(.L__gpr_num_\rt))
956 __emit_inst(0xd5000000|(\sreg)|(.L__gpr_num_\rt))
969 __emit_inst(0xd5200000|(\\sreg)|(.L__gpr_num_\\rt)) \
975 __emit_inst(0xd5000000|(\\sreg)|(.L__gpr_num_\\rt)) \
1000 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \
1012 } while (0)
1020 asm volatile(__mrs_s("%0", r) : "=r" (__val)); \
1027 } while (0)
1031 * set mask are set. Other bits are left as-is.
1038 } while (0)
1045 } while (0)