Lines Matching +full:0 +full:xffa50000
26 #size-cells = <0>;
28 cpu0: cpu@0 {
33 reg = <0x0>;
41 reg = <0x1>;
50 reg = <0x2>;
59 reg = <0x3>;
67 CPU_SLEEP_0: cpu-sleep-0 {
69 arm,psci-suspend-param = <0x40000000>;
106 interrupts = <0 35 4>;
107 xlnx,ipi-id = <0>;
113 reg = <0x0 0xff9905c0 0x0 0x20>,
114 <0x0 0xff9905e0 0x0 0x20>,
115 <0x0 0xff990e80 0x0 0x20>,
116 <0x0 0xff990ea0 0x0 0x20>;
134 interrupts = <0 143 4>,
135 <0 144 4>,
136 <0 145 4>,
137 <0 146 4>;
154 interrupts = <0 35 4>;
155 mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;
164 soc_revision: soc_revision@0 {
165 reg = <0x0 0x4>;
192 interrupts = <1 13 0xf08>,
193 <1 14 0xf08>,
194 <1 11 0xf08>,
195 <1 10 0xf08>;
216 reg = <0x0 0xff060000 0x0 0x1000>;
217 interrupts = <0 23 4>;
219 tx-fifo-depth = <0x40>;
220 rx-fifo-depth = <0x40>;
228 reg = <0x0 0xff070000 0x0 0x1000>;
229 interrupts = <0 24 4>;
231 tx-fifo-depth = <0x40>;
232 rx-fifo-depth = <0x40>;
239 reg = <0x0 0xfd6e0000 0x0 0x9000>;
240 ranges = <0x0 0x0 0xfd6e0000 0x10000>;
246 reg = <0x9000 0x5000>;
248 interrupts = <0 123 4>,
249 <0 123 4>,
250 <0 123 4>,
251 <0 123 4>,
252 <0 123 4>;
260 reg = <0x0 0xfd500000 0x0 0x1000>;
262 interrupts = <0 124 4>;
266 iommus = <&smmu 0x14e8>;
273 reg = <0x0 0xfd510000 0x0 0x1000>;
275 interrupts = <0 125 4>;
279 iommus = <&smmu 0x14e9>;
286 reg = <0x0 0xfd520000 0x0 0x1000>;
288 interrupts = <0 126 4>;
292 iommus = <&smmu 0x14ea>;
299 reg = <0x0 0xfd530000 0x0 0x1000>;
301 interrupts = <0 127 4>;
305 iommus = <&smmu 0x14eb>;
312 reg = <0x0 0xfd540000 0x0 0x1000>;
314 interrupts = <0 128 4>;
318 iommus = <&smmu 0x14ec>;
325 reg = <0x0 0xfd550000 0x0 0x1000>;
327 interrupts = <0 129 4>;
331 iommus = <&smmu 0x14ed>;
338 reg = <0x0 0xfd560000 0x0 0x1000>;
340 interrupts = <0 130 4>;
344 iommus = <&smmu 0x14ee>;
351 reg = <0x0 0xfd570000 0x0 0x1000>;
353 interrupts = <0 131 4>;
357 iommus = <&smmu 0x14ef>;
363 #address-cells = <0>;
365 reg = <0x0 0xf9010000 0x0 0x10000>,
366 <0x0 0xf9020000 0x0 0x20000>,
367 <0x0 0xf9040000 0x0 0x20000>,
368 <0x0 0xf9060000 0x0 0x20000>;
371 interrupts = <1 9 0xf04>;
381 reg = <0x0 0xffa80000 0x0 0x1000>;
383 interrupts = <0 77 4>;
387 iommus = <&smmu 0x868>;
394 reg = <0x0 0xffa90000 0x0 0x1000>;
396 interrupts = <0 78 4>;
400 iommus = <&smmu 0x869>;
407 reg = <0x0 0xffaa0000 0x0 0x1000>;
409 interrupts = <0 79 4>;
413 iommus = <&smmu 0x86a>;
420 reg = <0x0 0xffab0000 0x0 0x1000>;
422 interrupts = <0 80 4>;
426 iommus = <&smmu 0x86b>;
433 reg = <0x0 0xffac0000 0x0 0x1000>;
435 interrupts = <0 81 4>;
439 iommus = <&smmu 0x86c>;
446 reg = <0x0 0xffad0000 0x0 0x1000>;
448 interrupts = <0 82 4>;
452 iommus = <&smmu 0x86d>;
459 reg = <0x0 0xffae0000 0x0 0x1000>;
461 interrupts = <0 83 4>;
465 iommus = <&smmu 0x86e>;
472 reg = <0x0 0xffaf0000 0x0 0x1000>;
474 interrupts = <0 84 4>;
478 iommus = <&smmu 0x86f>;
484 reg = <0x0 0xfd070000 0x0 0x30000>;
486 interrupts = <0 112 4>;
492 reg = <0x0 0xff100000 0x0 0x1000>;
495 interrupts = <0 14 4>;
497 #size-cells = <0>;
498 iommus = <&smmu 0x872>;
506 interrupts = <0 57 4>, <0 57 4>;
507 reg = <0x0 0xff0b0000 0x0 0x1000>;
510 #size-cells = <0>;
511 iommus = <&smmu 0x874>;
521 interrupts = <0 59 4>, <0 59 4>;
522 reg = <0x0 0xff0c0000 0x0 0x1000>;
525 #size-cells = <0>;
526 iommus = <&smmu 0x875>;
536 interrupts = <0 61 4>, <0 61 4>;
537 reg = <0x0 0xff0d0000 0x0 0x1000>;
540 #size-cells = <0>;
541 iommus = <&smmu 0x876>;
551 interrupts = <0 63 4>, <0 63 4>;
552 reg = <0x0 0xff0e0000 0x0 0x1000>;
555 #size-cells = <0>;
556 iommus = <&smmu 0x877>;
565 #address-cells = <0>;
566 #gpio-cells = <0x2>;
569 interrupts = <0 16 4>;
572 reg = <0x0 0xff0a0000 0x0 0x1000>;
580 interrupts = <0 17 4>;
581 reg = <0x0 0xff020000 0x0 0x1000>;
583 #size-cells = <0>;
591 interrupts = <0 18 4>;
592 reg = <0x0 0xff030000 0x0 0x1000>;
594 #size-cells = <0>;
607 interrupts = <0 118 4>,
608 <0 117 4>,
609 <0 116 4>,
610 <0 115 4>, /* MSI_1 [63...32] */
611 <0 114 4>; /* MSI_0 [31...0] */
615 reg = <0x0 0xfd0e0000 0x0 0x1000>,
616 <0x0 0xfd480000 0x0 0x1000>,
617 <0x80 0x00000000 0x0 0x1000000>;
619 …ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-pre…
620 …<0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable mem…
621 bus-range = <0x00 0xff>;
622 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
623 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
624 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
625 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
626 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
627 iommus = <&smmu 0x4d0>;
631 #address-cells = <0>;
640 interrupts = <0 15 4>;
643 reg = <0x0 0xff0f0000 0x0 0x1000>,
644 <0x0 0xc0000000 0x0 0x8000000>;
646 #size-cells = <0>;
647 iommus = <&smmu 0x873>;
654 reg = <0x0 0xfd400000 0x0 0x40000>,
655 <0x0 0xfd3d0000 0x0 0x1000>;
663 reg = <0x0 0xffa60000 0x0 0x100>;
665 interrupts = <0 26 4>, <0 27 4>;
667 calibration = <0x7FFF>;
673 reg = <0x0 0xfd0c0000 0x0 0x2000>;
675 interrupts = <0 133 4>;
678 iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
679 <&smmu 0x4c2>, <&smmu 0x4c3>;
686 interrupts = <0 48 4>;
687 reg = <0x0 0xff160000 0x0 0x1000>;
689 iommus = <&smmu 0x870>;
699 interrupts = <0 49 4>;
700 reg = <0x0 0xff170000 0x0 0x1000>;
702 iommus = <&smmu 0x871>;
710 reg = <0x0 0xfd800000 0x0 0x20000>;
715 interrupts = <0 155 4>,
716 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
717 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
718 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
719 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
726 interrupts = <0 19 4>;
727 reg = <0x0 0xff040000 0x0 0x1000>;
730 #size-cells = <0>;
738 interrupts = <0 20 4>;
739 reg = <0x0 0xff050000 0x0 0x1000>;
742 #size-cells = <0>;
750 interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
751 reg = <0x0 0xff110000 0x0 0x1000>;
760 interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
761 reg = <0x0 0xff120000 0x0 0x1000>;
770 interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
771 reg = <0x0 0xff130000 0x0 0x1000>;
780 interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
781 reg = <0x0 0xff140000 0x0 0x1000>;
790 interrupts = <0 21 4>;
791 reg = <0x0 0xff000000 0x0 0x1000>;
800 interrupts = <0 22 4>;
801 reg = <0x0 0xff010000 0x0 0x1000>;
811 reg = <0x0 0xff9d0000 0x0 0x100>;
821 reg = <0x0 0xfe200000 0x0 0x40000>;
824 interrupts = <0 65 4>, <0 69 4>;
826 iommus = <&smmu 0x860>;
827 snps,quirk-frame-length-adjustment = <0x20>;
837 reg = <0x0 0xff9e0000 0x0 0x100>;
847 reg = <0x0 0xfe300000 0x0 0x40000>;
850 interrupts = <0 70 4>, <0 74 4>;
852 iommus = <&smmu 0x861>;
853 snps,quirk-frame-length-adjustment = <0x20>;
862 interrupts = <0 113 1>;
863 reg = <0x0 0xfd4d0000 0x0 0x1000>;
872 interrupts = <0 52 1>;
873 reg = <0x0 0xff150000 0x0 0x1000>;
881 interrupts = <0 56 4>;
882 reg = <0x0 0xffa50000 0x0 0x800>;
886 ranges = <0 0 0xffa50800 0x800>;
888 ams_ps: ams_ps@0 {
891 reg = <0x0 0x400>;
897 reg = <0x400 0x400>;
899 #size-cells = <0>;
906 reg = <0x0 0xfd4c0000 0x0 0x1000>;
907 interrupts = <0 122 4>;
917 reg = <0x0 0xfd4a0000 0x0 0x1000>,
918 <0x0 0xfd4aa000 0x0 0x1000>,
919 <0x0 0xfd4ab000 0x0 0x1000>,
920 <0x0 0xfd4ac000 0x0 0x1000>;
922 interrupts = <0 119 4>;