Lines Matching +full:io +full:- +full:channel +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2021, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
21 compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
38 stdout-path = "serial0:115200n8";
47 gpio-keys {
48 compatible = "gpio-keys";
50 switch-19 {
54 wakeup-source;
60 compatible = "gpio-leds";
61 heartbeat-led {
64 linux,default-trigger = "heartbeat";
68 ina226-u67 {
69 compatible = "iio-hwmon";
70 io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>;
72 ina226-u59 {
73 compatible = "iio-hwmon";
74 io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>;
76 ina226-u61 {
77 compatible = "iio-hwmon";
78 io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;
80 ina226-u60 {
81 compatible = "iio-hwmon";
82 io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;
84 ina226-u64 {
85 compatible = "iio-hwmon";
86 io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;
88 ina226-u69 {
89 compatible = "iio-hwmon";
90 io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>;
92 ina226-u66 {
93 compatible = "iio-hwmon";
94 io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>;
96 ina226-u65 {
97 compatible = "iio-hwmon";
98 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
100 ina226-u63 {
101 compatible = "iio-hwmon";
102 io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;
104 ina226-u3 {
105 compatible = "iio-hwmon";
106 io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>;
108 ina226-u71 {
109 compatible = "iio-hwmon";
110 io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>;
112 ina226-u77 {
113 compatible = "iio-hwmon";
114 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
116 ina226-u73 {
117 compatible = "iio-hwmon";
118 io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>;
120 ina226-u79 {
121 compatible = "iio-hwmon";
122 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
127 compatible = "fixed-clock";
128 #clock-cells = <0>;
129 clock-frequency = <48000000>;
171 phy-handle = <&phy0>;
172 phy-mode = "rgmii-id";
173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_gem3_default>;
175 phy0: ethernet-phy@c {
177 ti,rx-internal-delay = <0x8>;
178 ti,tx-internal-delay = <0xa>;
179 ti,fifo-depth = <0x1>;
180 ti,dp83867-rxctrl-strap-quirk;
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_gpio_default>;
192 clock-frequency = <400000>;
193 pinctrl-names = "default", "gpio";
194 pinctrl-0 = <&pinctrl_i2c0_default>;
195 pinctrl-1 = <&pinctrl_i2c0_gpio>;
196 scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
197 sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
202 gpio-controller; /* interrupt not connected */
203 #gpio-cells = <2>;
207 * 0 - MAX6643_OT_B
208 * 1 - MAX6643_FANFAIL_B
209 * 2 - MIO26_PMU_INPUT_LS
210 * 4 - SFP_SI5382_INT_ALM
211 * 5 - IIC_MUX_RESET_B
212 * 6 - GEM3_EXP_RESET_B
213 * 10 - FMCP_HSPC_PRSNT_M2C_B
214 * 11 - CLK_SPI_MUX_SEL0
215 * 12 - CLK_SPI_MUX_SEL1
216 * 16 - IRPS5401_ALERT_B
217 * 17 - INA226_PMBUS_ALERT
218 * 3, 7, 13-15 - not connected
222 i2c-mux@75 { /* u23 */
224 #address-cells = <1>;
225 #size-cells = <0>;
228 #address-cells = <1>;
229 #size-cells = <0>;
235 #io-channel-cells = <1>;
236 label = "ina226-u67";
238 shunt-resistor = <2000>;
242 #io-channel-cells = <1>;
243 label = "ina226-u59";
245 shunt-resistor = <5000>;
249 #io-channel-cells = <1>;
250 label = "ina226-u61";
252 shunt-resistor = <5000>;
256 #io-channel-cells = <1>;
257 label = "ina226-u60";
259 shunt-resistor = <5000>;
263 #io-channel-cells = <1>;
264 label = "ina226-u64";
266 shunt-resistor = <5000>;
270 #io-channel-cells = <1>;
271 label = "ina226-u69";
273 shunt-resistor = <2000>;
277 #io-channel-cells = <1>;
278 label = "ina226-u66";
280 shunt-resistor = <5000>;
284 #io-channel-cells = <1>;
285 label = "ina226-u65";
287 shunt-resistor = <5000>;
291 #io-channel-cells = <1>;
292 label = "ina226-u63";
294 shunt-resistor = <5000>;
298 #io-channel-cells = <1>;
299 label = "ina226-u3";
301 shunt-resistor = <5000>;
305 #io-channel-cells = <1>;
306 label = "ina226-u71";
308 shunt-resistor = <5000>;
312 #io-channel-cells = <1>;
313 label = "ina226-u77";
315 shunt-resistor = <5000>;
319 #io-channel-cells = <1>;
320 label = "ina226-u73";
322 shunt-resistor = <5000>;
326 #io-channel-cells = <1>;
327 label = "ina226-u79";
329 shunt-resistor = <5000>;
333 #address-cells = <1>;
334 #size-cells = <0>;
339 #address-cells = <1>;
340 #size-cells = <0>;
342 irps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */
346 irps5401_44: irps5401@44 { /* IRPS5401 - u55 */
350 irps5401_45: irps5401@45 { /* IRPS5401 - u57 */
362 #address-cells = <1>;
363 #size-cells = <0>;
372 clock-frequency = <400000>;
373 pinctrl-names = "default", "gpio";
374 pinctrl-0 = <&pinctrl_i2c1_default>;
375 pinctrl-1 = <&pinctrl_i2c1_gpio>;
376 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
377 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
379 i2c-mux@74 { /* u26 */
381 #address-cells = <1>;
382 #size-cells = <0>;
385 #address-cells = <1>;
386 #size-cells = <0>;
391 * 0 - 256B address 0x54
392 * 256B - 512B address 0x55
393 * 512B - 768B address 0x56
394 * 768B - 1024B address 0x57
402 #address-cells = <1>;
403 #size-cells = <0>;
405 si5341: clock-generator@36 { /* SI5341 - u46 */
408 #clock-cells = <2>;
409 #address-cells = <1>;
410 #size-cells = <0>;
412 clock-names = "xtal";
413 clock-output-names = "si5341";
416 /* refclk0 for PS-GT, used for DP */
418 always-on;
421 /* refclk2 for PS-GT, used for USB3 */
423 always-on;
426 /* refclk3 for PS-GT, used for SATA */
428 always-on;
433 always-on;
438 always-on;
443 always-on;
448 #address-cells = <1>;
449 #size-cells = <0>;
451 si570_1: clock-generator@5d { /* USER SI570 - u47 */
452 #clock-cells = <0>;
455 temperature-stability = <50>;
456 factory-fout = <300000000>;
457 clock-frequency = <300000000>;
458 clock-output-names = "si570_user";
462 #address-cells = <1>;
463 #size-cells = <0>;
465 si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */
466 #clock-cells = <0>;
469 temperature-stability = <50>;
470 factory-fout = <156250000>;
471 clock-frequency = <156250000>;
472 clock-output-names = "si570_mgt";
476 #address-cells = <1>;
477 #size-cells = <0>;
479 /* SI5382 - u48 */
482 #address-cells = <1>;
483 #size-cells = <0>;
485 sc18is603@2f { /* sc18is602 - u93 */
491 * LMK04208 - u90 or
492 * LMX2594 - u102 or
493 * LMX2594 - u103 or
494 * LMX2594 - u104
499 #address-cells = <1>;
500 #size-cells = <0>;
507 i2c-mux@75 {
509 #address-cells = <1>;
510 #size-cells = <0>;
514 #address-cells = <1>;
515 #size-cells = <0>;
520 #address-cells = <1>;
521 #size-cells = <0>;
526 #address-cells = <1>;
527 #size-cells = <0>;
532 #address-cells = <1>;
533 #size-cells = <0>;
538 #address-cells = <1>;
539 #size-cells = <0>;
544 #address-cells = <1>;
545 #size-cells = <0>;
550 #address-cells = <1>;
551 #size-cells = <0>;
556 #address-cells = <1>;
557 #size-cells = <0>;
566 pinctrl_i2c0_default: i2c0-default {
574 bias-pull-up;
575 slew-rate = <SLEW_RATE_SLOW>;
576 power-source = <IO_STANDARD_LVCMOS18>;
580 pinctrl_i2c0_gpio: i2c0-gpio {
588 slew-rate = <SLEW_RATE_SLOW>;
589 power-source = <IO_STANDARD_LVCMOS18>;
593 pinctrl_i2c1_default: i2c1-default {
601 bias-pull-up;
602 slew-rate = <SLEW_RATE_SLOW>;
603 power-source = <IO_STANDARD_LVCMOS18>;
607 pinctrl_i2c1_gpio: i2c1-gpio {
615 slew-rate = <SLEW_RATE_SLOW>;
616 power-source = <IO_STANDARD_LVCMOS18>;
620 pinctrl_uart0_default: uart0-default {
628 slew-rate = <SLEW_RATE_SLOW>;
629 power-source = <IO_STANDARD_LVCMOS18>;
632 conf-rx {
634 bias-high-impedance;
637 conf-tx {
639 bias-disable;
643 pinctrl_usb0_default: usb0-default {
651 slew-rate = <SLEW_RATE_SLOW>;
652 power-source = <IO_STANDARD_LVCMOS18>;
655 conf-rx {
657 bias-high-impedance;
660 conf-tx {
663 bias-disable;
667 pinctrl_gem3_default: gem3-default {
675 slew-rate = <SLEW_RATE_SLOW>;
676 power-source = <IO_STANDARD_LVCMOS18>;
679 conf-rx {
682 bias-high-impedance;
683 low-power-disable;
686 conf-tx {
689 bias-disable;
690 low-power-enable;
693 mux-mdio {
698 conf-mdio {
700 slew-rate = <SLEW_RATE_SLOW>;
701 power-source = <IO_STANDARD_LVCMOS18>;
702 bias-disable;
706 pinctrl_sdhci1_default: sdhci1-default {
714 slew-rate = <SLEW_RATE_SLOW>;
715 power-source = <IO_STANDARD_LVCMOS18>;
716 bias-disable;
719 mux-cd {
724 conf-cd {
726 bias-high-impedance;
727 bias-pull-up;
728 slew-rate = <SLEW_RATE_SLOW>;
729 power-source = <IO_STANDARD_LVCMOS18>;
733 pinctrl_gpio_default: gpio-default {
741 slew-rate = <SLEW_RATE_SLOW>;
742 power-source = <IO_STANDARD_LVCMOS18>;
745 mux-msp {
750 conf-msp {
752 slew-rate = <SLEW_RATE_SLOW>;
753 power-source = <IO_STANDARD_LVCMOS18>;
756 conf-pull-up {
758 bias-pull-up;
761 conf-pull-none {
763 bias-disable;
772 clock-names = "ref1", "ref2", "ref3";
778 compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */
779 #address-cells = <1>;
780 #size-cells = <1>;
782 spi-tx-bus-width = <1>;
783 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
784 spi-max-frequency = <108000000>; /* Based on DC1 spec */
795 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
796 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
797 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
798 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
799 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
800 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
801 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
802 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
803 phy-names = "sata-phy";
810 pinctrl-names = "default";
811 pinctrl-0 = <&pinctrl_sdhci1_default>;
812 disable-wp;
816 no-1-8-v;
817 xlnx,mio-bank = <1>;
822 pinctrl-names = "default";
823 pinctrl-0 = <&pinctrl_uart0_default>;
829 pinctrl-names = "default";
830 pinctrl-0 = <&pinctrl_usb0_default>;
831 phy-names = "usb3-phy";
839 maximum-speed = "super-speed";
848 phy-names = "dp-phy0", "dp-phy1";